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ADN2812ACPZ-RL7 PDF预览

ADN2812ACPZ-RL7

更新时间: 2024-02-08 17:35:38
品牌 Logo 应用领域
亚德诺 - ADI ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式时钟
页数 文件大小 规格书
28页 409K
描述
Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery

ADN2812ACPZ-RL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.12
应用程序:SONET;SDHJESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
湿度敏感等级:3功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC32,.2SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.259 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
Base Number Matches:1

ADN2812ACPZ-RL7 数据手册

 浏览型号ADN2812ACPZ-RL7的Datasheet PDF文件第2页浏览型号ADN2812ACPZ-RL7的Datasheet PDF文件第3页浏览型号ADN2812ACPZ-RL7的Datasheet PDF文件第4页浏览型号ADN2812ACPZ-RL7的Datasheet PDF文件第5页浏览型号ADN2812ACPZ-RL7的Datasheet PDF文件第6页浏览型号ADN2812ACPZ-RL7的Datasheet PDF文件第7页 
Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and  
Data Recovery IC with Integrated Limiting Amp  
Data Sheet  
ADN2812  
FEATURES  
GENERAL DESCRIPTION  
Serial data input: 12.3 Mb/s to 2.7 Gb/s  
Exceeds SONET requirements for jitter transfer/  
generation/tolerance  
Quantizer sensitivity: 6 mV typical  
Adjustable slice level: 100 mV  
Patented clock recovery architecture  
Loss of signal (LOS) detect range: 3 mV to 15 mV  
Independent slice level adjust and LOS detector  
No reference clock required  
The ADN2812 provides the receiver functions of quantization,  
signal level detect, and clock and data recovery for continuous  
data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 auto-  
matically locks to all data rates without the need for an external  
reference clock or programming. All SONET jitter requirements  
are met, including jitter transfer, jitter generation, and jitter  
tolerance. All specifications are quoted for −40°C to +85°C  
ambient temperature, unless otherwise noted.  
This device, together with a PIN diode and a TIA preamplifier,  
can implement a highly integrated, low cost, low power fiber  
optic receiver.  
Loss of lock indicator  
I2C interface to access optional features  
Single-supply operation: 3.3 V  
The receiver front end, loss of signal (LOS) detector circuit  
indicates when the input signal level has fallen below a user-  
adjustable threshold. The LOS detect circuit has hysteresis to  
prevent chatter at the output.  
Low power: 750 mW typical  
5 mm × 5 mm 32-lead LFCSP  
APPLICATIONS  
SONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates  
Fibre Channel, 2× Fibre Channel, GbE, HDTV  
WDM transponders  
The ADN2812 is available in a compact 5 mm × 5 mm 32-lead  
lead frame chip scale package (LFCSP).  
Regenerators/repeaters  
Test equipment  
Broadband cross-connects and routers  
FUNCTIONAL BLOCK DIAGRAM  
REFCLKP/N  
(OPTIONAL)  
LOL  
CF1  
CF2 VCC  
VEE  
2
LOOP  
FILTER  
FREQUENCY  
DETECT  
SLICEP/N  
PIN  
PHASE  
SHIFTER  
PHASE  
DETECT  
LOOP  
FILTER  
QUANTIZER  
VCO  
NIN  
VREF  
LOS  
DETECT  
DATA  
RE-TIMING  
2
2
THRADJ  
LOS  
DATAOUTP/N  
CLKOUTP/N  
Figure 1.  
Rev. E  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibilityis assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.  
 
 
 
 

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