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ADMC300BST PDF预览

ADMC300BST

更新时间: 2024-02-04 00:36:18
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器电机时钟
页数 文件大小 规格书
42页 296K
描述
High Performance DSP-Based Motor Controller

ADMC300BST 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-80
针数:80Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.83地址总线宽度:
桶式移位器:YES边界扫描:NO
最大时钟频率:12.5 MHz外部数据总线宽度:
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PQFP-G80JESD-609代码:e0
长度:14 mm低功率模式:YES
端子数量:80最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):220
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADMC300BST 数据手册

 浏览型号ADMC300BST的Datasheet PDF文件第2页浏览型号ADMC300BST的Datasheet PDF文件第3页浏览型号ADMC300BST的Datasheet PDF文件第4页浏览型号ADMC300BST的Datasheet PDF文件第5页浏览型号ADMC300BST的Datasheet PDF文件第6页浏览型号ADMC300BST的Datasheet PDF文件第7页 
High Performance DSP-Based  
Motor Controller  
a
ADMC300  
TARGET APPLICATIONS  
Industrial Drives, Servo Drives, Variable Speed Drives,  
Electric Vehicles  
Flexible Synchronization of ADC and PWM Subsystems  
Independent Offset Calibration for Each Channel  
Two Dedicated ADC Interrupts  
Internal 2.5 V Reference  
FEATURES  
Three Multiplexer Control Pins for External Expansion  
Hardware or Software Convert Start  
Individual Power-Down for Each Bank  
Three-Phase PWM Generation Subsystem  
16-Bit Dedicated PWM Generator  
25 MIPS Fixed-Point DSP Core  
Single Cycle Instruction Execution (40 ns)  
ADSP-2100 Family Code Compatible  
Independent Computational Units  
ALU  
Multiplier/Accumulator  
Barrel Shifter  
Multifunction Instructions  
Single Cycle Context Switch  
Powerful Program Sequencer  
Zero Overhead Looping  
Conditional Instruction Execution  
Two Independent Data Address Generators  
Memory Configuration  
4K 24-Bit Program Memory RAM  
2K 24-Bit Program Memory ROM  
1K 16-Bit Data Memory RAM  
High-Resolution Multichannel ADC System  
Five Independent 16-Bit Sigma-Delta ADCs  
76 dB SNR Typical (ENOB > 12 Bits)  
Arranged in Two Independently Clocked Banks  
Differential or Single-Ended Inputs  
Programmable Sample Frequency to 32.5 kHz  
Edge Resolution to 40 ns  
Programmable Dead Time  
Programmable Minimum Pulsewidth  
Double Update Mode Allows Duty Cycle  
Adjustment on Half Cycle Boundaries  
Special Features for Brushless DC Motors  
Hardwired Polarity Control  
External Dedicated Asynchronous Shutdown Pin  
(PWMTRIP)  
Additional Shutdown Pins in I/O System  
Individual Enable/Disable of Each Output  
High Frequency Chopping Mode  
Transparent Transition to Overmodulation  
Range with Duty Cycles of 100%  
Programmable Interrupt Controller Manages Priority  
and Masking of 11 Peripheral Interrupts  
(Continued on Page 7)  
FUNCTIONAL BLOCK DIAGRAM  
ADSP-2100 BASE  
ARCHITECTURE  
MOTOR CONTROL  
PERIPHERALS  
PROGRAM  
ROM  
2K 24  
3
2
12  
MEMORY  
DATA  
ADDRESS  
WATCH-  
DOG  
PROGRAM  
INTERRUPT  
CONTROLLER  
EVENT  
CAPTURE  
TIMERS  
DATA  
RAM  
1K 16  
PROGRAM  
RAM  
4K 24  
GENERATORS  
ENCODER  
INTERFACE  
DIGITAL  
I/O  
PROGRAM  
SEQUENCER  
TIMER  
DAG 1 DAG 2  
PROGRAM MEMORY ADDRESS BUS  
DATA MEMORY ADDRESS BUS  
PROGRAM MEMORY DATA BUS  
DATA MEMORY DATA BUS  
SERIAL PORTS  
SPORT 0 SPORT 1  
PWM  
GENERATION  
INTERVAL  
TIMER  
AUXILIARY  
PWM  
SIGMA-DELTA  
ADCs  
ARITHMETIC UNITS  
ALU  
MAC  
SHIFTER  
5
6
2
10  
7
REV. B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  

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