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ADF4350BCPZ

更新时间： 2024-01-15 12:09:57
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路信息通信管理
页数 文件大小 规格书
28页 700K
描述
Wideband Synthesizer with Integrated VCO

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ADF4350BCPZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：32
Reach Compliance Code：unknown风险等级：5.43
Is Samacsys：N模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm湿度敏感等级：NOT APPLICABLE
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：5 mmBase Number Matches：1

ADF4350BCPZ 数据手册

 浏览型号ADF4350BCPZ的Datasheet PDF文件第2页浏览型号ADF4350BCPZ的Datasheet PDF文件第3页浏览型号ADF4350BCPZ的Datasheet PDF文件第4页浏览型号ADF4350BCPZ的Datasheet PDF文件第5页浏览型号ADF4350BCPZ的Datasheet PDF文件第6页浏览型号ADF4350BCPZ的Datasheet PDF文件第7页 
Wideband Synthesizer with Integrated VCO  
ADF4350  
FEATURES  
GENERAL DESCRIPTION  
Output frequency range: 137.5 MHz to 4400 MHz  
Fractional-N synthesizer and integer-N synthesizer  
Low phase noise VCO  
Programmable divide-by-1/-2/-4/-8/-16 output  
Typical rms jitter: 0.5 ps rms  
Power supply: 3.0 V to 3.6 V  
Logic compatibility: 1.8 V  
Programmable dual-modulus prescaler of 4/5 or 8/9  
Programmable output power level  
RF output mute function  
The ADF4350 allows implementation of fractional-N or  
integer-N phase-locked loop (PLL) frequency synthesizers  
if used with an external loop filter and external reference  
frequency.  
The ADF4350 has an integrated voltage controlled oscillator  
(VCO) with a fundamental output frequency ranging from  
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16  
circuits allow the user to generate RF output frequencies as low  
as 137.5 MHz. For applications that require isolation, the RF  
output stage can be muted. The mute function is both pin- and  
software-controllable. An auxiliary RF output is also available,  
which can be powered down if not in use.  
3-wire serial interface  
Analog and digital lock detect  
Switched bandwidth fast-lock mode  
Cycle slip reduction  
Control of all the on-chip registers is through a simple 3-wire  
interface. The device operates with a power supply ranging  
from 3.0 V to 3.6 V and can be powered down when not in use.  
APPLICATIONS  
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,  
GSM, PCS, DCS, DECT)  
Test equipment  
Wireless LANs, CATV equipment  
Clock generation  
FUNCTIONAL BLOCK DIAGRAM  
SDV  
AV  
DV  
V
R
V
VCO  
DD  
DD  
DD  
P
SET  
MULTIPLEXER  
MUXOUT  
10-BIT R  
COUNTER  
÷2  
DIVIDER  
×2  
REF  
IN  
DOUBLER  
LOCK  
DETECT  
SW  
LD  
FL SWITCH  
O
CLK  
DATA  
LE  
DATA REGISTER  
FUNCTION  
LATCH  
CHARGE  
PUMP  
CP  
OUT  
PHASE  
COMPARATOR  
V
V
TUNE  
REF  
V
VCO  
COM  
CORE  
TEMP  
INTEGER  
REG  
FRACTION  
REG  
MODULUS  
REG  
RF  
RF  
A+  
A–  
OUT  
OUTPUT  
STAGE  
THIRD-ORDER  
FRACTIONAL  
INTERPOLATOR  
÷1/2/4/8/16  
OUT  
PDBRF  
RF  
RF  
B+  
OUTPUT  
STAGE  
OUT  
N COUNTER  
B–  
OUT  
MULTIPLEXER  
SD  
ADF4350  
AGND  
DGND  
CP  
A
GNDVCO  
CE  
GND  
GND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  
 
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