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ADF4251 PDF预览

ADF4251

更新时间: 2024-01-28 07:04:39
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 425K
描述
Dual Fractional-N/Integer-N Frequency Synthesizer

ADF4251 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:VQCCN, LCC24,.16SQ,20
针数:24Reach Compliance Code:not_compliant
ECCN代码:5A991.BHTS代码:8542.39.00.01
风险等级:5.72Is Samacsys:N
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:S-XQCC-N24
JESD-609代码:e0长度:4 mm
湿度敏感等级:3功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:VQCCN封装等效代码:LCC24,.16SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):240电源:3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:4 mmBase Number Matches:1

ADF4251 数据手册

 浏览型号ADF4251的Datasheet PDF文件第2页浏览型号ADF4251的Datasheet PDF文件第3页浏览型号ADF4251的Datasheet PDF文件第4页浏览型号ADF4251的Datasheet PDF文件第5页浏览型号ADF4251的Datasheet PDF文件第6页浏览型号ADF4251的Datasheet PDF文件第7页 
Dual Fractional-N/Integer-N  
Frequency Synthesizer  
ADF4251  
FEATURES  
GENERAL DESCRIPTION  
3.0 GHz Fractional-N/1.2 GHz Integer-N  
2.7 V to 3.3 V Power Supply  
Separate VP Allows Extended Tuning Voltage to 5 V  
Programmable Dual Modulus Prescaler  
RF: 4/5, 8/9  
IF: 8/9, 16/17, 32/33, 64/65  
Programmable Charge Pump Currents  
3-Wire Serial Interface  
Digital Lock Detect  
Power-Down Mode  
Programmable Modulus on Fractional-N Synthesizer  
Trade-Off Noise versus Spurious Performance  
Software and Hardware Power-Down  
The ADF4251 is a dual fractional-N/integer-N frequency  
synthesizer that can be used to implement local oscillators  
(LO) in the upconversion and downconversion sections of  
wireless receivers and transmitters. Both the RF and IF syn-  
thesizers consist of a low noise digital PFD (phase frequency  
detector), a precision charge pump, and a programmable refer-  
ence divider. The RF synthesizer has a -based fractional  
interpolator that allows programmable fractional-N division.  
The IF synthesizer has programmable integer-N counters. A  
complete PLL (phase-locked loop) can be implemented if the  
synthesizer is used with an external loop filter and VCO (volt-  
age controlled oscillator).  
Control of all the on-chip registers is via a simple 3-wire inter-  
face. The devices operate with a power supply ranging from  
2.7 V to 3.3 V and can be powered down when not in use.  
APPLICATIONS  
Base Stations for Mobile Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA,  
PHS)  
Wireless LANs  
Communications Test Equipment  
CATV Equipment  
FUNCTIONAL BLOCK DIAGRAM  
V
1
V
2
V
3
DV  
V 1  
V 2  
R
SET  
DD  
DD  
DD  
DD  
P
P
CE  
CP  
ADF4251  
REFERENCE  
4-BIT R  
2  
COUNTER  
REF  
PHASE  
IN  
DOUBLER  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
RF  
LOCK  
OUTPUT  
MUXOUT  
DETECT  
MUX  
RF  
RF  
A
IN  
FRACTIONAL N  
RF DIVIDER  
B
IN  
CLK  
DATA  
LE  
24-BIT  
DATA  
REGISTER  
INTEGER N  
IF DIVIDER  
IF  
IF  
B
IN  
FROM  
REFIN  
A
IN  
PHASE  
CHARGE  
PUMP  
CP  
FREQUENCY  
DETECTOR  
IF  
2  
15-BIT R  
DOUBLER  
COUNTER  
A
1
A
2
D
CP  
1
CP  
2
GND  
GND  
GND  
GND  
GND  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  

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