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ADF4193BCPZ-RL7 PDF预览

ADF4193BCPZ-RL7

更新时间: 2024-02-24 08:52:12
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路信息通信管理
页数 文件大小 规格书
28页 595K
描述
Low Phase Noise, Fast Settling PLL Frequency Synthesizer

ADF4193BCPZ-RL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
Is Samacsys:N模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:PLL or Frequency Synthesis Circuits
最大供电电流 (Isup):27 mA最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:5 mmBase Number Matches:1

ADF4193BCPZ-RL7 数据手册

 浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第2页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第3页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第4页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第5页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第6页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第7页 
Low Phase Noise, Fast Settling PLL  
Frequency Synthesizer  
ADF4193  
FEATURES  
GENERAL DESCRIPTION  
New, fast settling, fractional-N PLL architecture  
Single PLL replaces ping-pong synthesizers  
Frequency hop across GSM band in 5 μs with phase settled  
by 20 μs  
0.5° rms phase error at 2 GHz RF output  
Digitally programmable output phase  
RF input range up to 3.5 GHz  
The ADF4193 frequency synthesizer can be used to implement  
local oscillators in the upconversion and downconversion  
sections of wireless receivers and transmitters. Its architecture  
is specifically designed to meet the GSM/EDGE lock time  
requirements for base stations. It consists of a low noise, digital  
phase frequency detector (PFD), and a precision differential  
charge pump. There is also a differential amplifier to convert  
the differential charge pump output to a single-ended voltage  
for the external voltage-controlled oscillator (VCO).  
3-wire serial interface  
On-chip, low noise differential amplifier  
Phase noise figure of merit: −216 dBc/Hz  
Loop filter design possible using ADI SimPLL  
The Σ-Δ based fractional interpolator, working with the N  
divider, allows programmable modulus fractional-N division.  
Additionally, the 4-bit reference (R) counter and on-chip  
frequency doubler allow selectable reference signal (REFIN)  
frequencies at the PFD input. A complete phase-locked loop  
(PLL) can be implemented if the synthesizer is used with an  
external loop filter and a VCO. The switching architecture  
ensures that the PLL settles inside the GSM time slot guard  
period, removing the need for a second PLL and associated  
isolation switches. This decreases cost, complexity, PCB area,  
shielding, and characterization on previous ping-pong GSM  
PLL architectures.  
APPLICATIONS  
GSM/EDGE base stations  
PHS base stations  
Instrumentation and test equipment  
FUNCTIONAL BLOCK DIAGRAM  
SDV  
DV  
1
DV  
2
DV  
3
AV  
1
V 1  
V 2  
V 3  
R
SET  
DD  
DD  
×2  
DD  
DD  
DD  
P
P
P
REFERENCE  
SW1  
CP  
4-BIT R  
COUNTER  
/2  
DIVIDER  
+
PHASE  
+
REF  
CHARGE  
PUMP  
OUT+  
IN  
FREQUENCY  
DETECTOR  
DOUBLER  
CP  
OUT–  
SW2  
CMR  
V
DD  
DGND  
HIGH Z  
LOCK DETECT  
DIFFERENTIAL  
AMPLIFIER  
AIN–  
AIN+  
+
OUTPUT  
MUX  
MUX  
OUT  
R
N
DIV  
DIV  
A
OUT  
N COUNTER  
SW3  
FRACTIONAL  
INTERPOLATOR  
RF  
RF  
IN+  
IN–  
CLK  
DATA  
LE  
24-BIT  
DATA  
REGISTER  
FRACTION  
REG  
MODULUS  
REG  
INTEGER  
REG  
ADF4193  
A
1
A
2
D
1
D
2
D
3
SD  
GND  
SW  
GND  
GND  
GND  
GND  
GND  
GND  
Figure 1.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 

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