Low Phase Noise, Fast Settling PLL
Frequency Synthesizer
ADF4193
FEATURES
GENERAL DESCRIPTION
New, fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
by 20 μs
0.5° rms phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
The ADF4193 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture
is specifically designed to meet the GSM/EDGE lock time
requirements for base stations. It consists of a low noise, digital
phase frequency detector (PFD), and a precision differential
charge pump. There is also a differential amplifier to convert
the differential charge pump output to a single-ended voltage
for the external voltage-controlled oscillator (VCO).
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
Loop filter design possible using ADI SimPLL
The Σ-Δ based fractional interpolator, working with the N
divider, allows programmable modulus fractional-N division.
Additionally, the 4-bit reference (R) counter and on-chip
frequency doubler allow selectable reference signal (REFIN)
frequencies at the PFD input. A complete phase-locked loop
(PLL) can be implemented if the synthesizer is used with an
external loop filter and a VCO. The switching architecture
ensures that the PLL settles inside the GSM time slot guard
period, removing the need for a second PLL and associated
isolation switches. This decreases cost, complexity, PCB area,
shielding, and characterization on previous ping-pong GSM
PLL architectures.
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment
FUNCTIONAL BLOCK DIAGRAM
SDV
DV
1
DV
2
DV
3
AV
1
V 1
V 2
V 3
R
SET
DD
DD
×2
DD
DD
DD
P
P
P
REFERENCE
SW1
CP
4-BIT R
COUNTER
/2
DIVIDER
+
PHASE
+
REF
CHARGE
PUMP
OUT+
IN
FREQUENCY
DETECTOR
DOUBLER
CP
–
OUT–
–
SW2
CMR
V
DD
DGND
HIGH Z
LOCK DETECT
DIFFERENTIAL
AMPLIFIER
AIN–
AIN+
–
+
OUTPUT
MUX
MUX
OUT
R
N
DIV
DIV
A
OUT
N COUNTER
SW3
FRACTIONAL
INTERPOLATOR
RF
RF
IN+
IN–
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION
REG
MODULUS
REG
INTEGER
REG
ADF4193
A
1
A
2
D
1
D
2
D
3
SD
GND
SW
GND
GND
GND
GND
GND
GND
Figure 1.
Rev. B
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