ADF4157

更新时间： 2024-02-06 16:17:37

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	404K
描述
High Resolution 6 GHz Fractional-N Frequency Synthesizer

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ADF4157 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	unknown	ECCN代码：	5A991.B
HTS代码：	8542.39.00.01	风险等级：	5.24
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3/5.5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	PLL or Frequency Synthesis Circuits	最大供电电流 (Isup)：	29 mA
最大供电电压 (Vsup)：	3.3 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	4.4 mm

ADF4157 数据手册

High Resolution 6 GHz Fractional-N

Frequency Synthesizer

ADF4157

FEATURES

GENERAL DESCRIPTION

RF bandwidth to 6 GHz

25-bit fixed modulus allows subhertz frequency resolution

2.7 V to 3.3 V power supply

Separate V_Pallows extended tuning voltage

Programmable charge pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with the following frequency synthesizers:

ADF4110/ADF4111/ADF4112/ADF4113/

ADF4106/ADF4153/ADF4154/ADF4156

Cycle slip reduction for faster lock times

The ADF4157 is a 6 GHz fractional-N frequency synthesizer

with a 25-bit fixed modulus, allowing subhertz frequency

resolution at 6 GHz. It consists of a low noise digital phase

frequency detector (PFD), a precision charge pump, and

a programmable reference divider. There is a Σ-Δ based

fractional interpolator to allow programmable fractional-N

division. The INT and FRAC registers define an overall

N divider, N = INT + (FRAC/2²⁵). The ADF4157 features cycle

slip reduction circuitry, which leads to faster lock times without

the need for modifications to the loop filter.

Control of all on-chip registers is via a simple 3-wire interface.

The device operates with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

APPLICATIONS

Satellite communications terminals, radar equipment

Instrumentation equipment

Personal mobile radio (PMR)

Base stations for mobile radio

Wireless handsets

FUNCTIONAL BLOCK DIAGRAM

SET

ADF4157

REFERENCE

4-BIT

R COUNTER

×2

REF

DOUBLER

÷2

DIVIDER

PHASE

CHARGE

PUMP

FREQUENCY

DETECTOR

–

HIGH Z

CSR

DGND

LOCK

DETECT

CURRENT

SETTING

OUTPUT

MUX

MUXOUT

OUT

RFCP4 RFCP3 RFCP2 RFCP1

DIV

N COUNTER

THIRD ORDER

FRACTIONAL

INTERPOLATOR

CLK

DATA

FRACTION MODULUS

INTEGER

REG

32-BIT

DATA

REG

AGND

DGND

CPGND

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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