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ADF4108BCPZ-RL7 PDF预览

ADF4108BCPZ-RL7

更新时间: 2024-01-11 05:36:01
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路
页数 文件大小 规格书
20页 440K
描述
PLL Frequency Synthesizer

ADF4108BCPZ-RL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:VQCCN, LCC20,.16SQ,20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.23
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:R-XQCC-N20
JESD-609代码:e3长度:4 mm
湿度敏感等级:3功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:VQCCN封装等效代码:LCC20,.16SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

ADF4108BCPZ-RL7 数据手册

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PLL Frequency Synthesizer  
ADF4108  
FEATURES  
GENERAL DESCRIPTION  
8.0 GHz bandwidth  
3.2 V to 3.6 V power supply  
Separate charge pump supply (VP) allows extended tuning  
voltage in 3.3 V systems  
Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or  
64/65  
Programmable charge pump currents  
Programmable antibacklash pulse width  
3-wire serial interface  
Analog and digital lock detect  
Hardware and software power-down mode  
Loop filter design possible with ADIsimPLL  
The ADF4108 frequency synthesizer can be used to implement  
local oscillators in the up-conversion and down-conversion  
sections of wireless receivers and transmitters. It consists of a  
low noise digital PFD (phase frequency detector), a precision  
charge pump, a programmable reference divider, programmable  
A and B counters, and a dual-modulus prescaler (P/P + 1). The  
A (6-bit) and B (13-bit) counters, in conjunction with the dual-  
modulus prescaler (P/P + 1), implement an N divider (N =  
BP + A). In addition, the 14-bit reference counter (R counter),  
allows selectable REFIN frequencies at the PFD input. A  
complete phase-locked loop (PLL) can be implemented if the  
synthesizer is used with an external loop filter and voltage  
controlled oscillator (VCO). Its very high bandwidth means  
that frequency doublers can be eliminated in many high  
frequency systems, simplifying system architecture and  
reducing cost.  
APPLICATIONS  
Broadband wireless access  
Satellite systems  
Instrumentation  
Wireless LANs  
Base stations for wireless radio  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DV  
R
SET  
V
CPGND  
DD  
DD  
P
REFERENCE  
14-BIT  
R COUNTER  
PHASE  
FREQUENCY  
DETECTOR  
REF  
CHARGE  
PUMP  
IN  
CP  
14  
R COUNTER  
LATCH  
LOCK  
DETECT  
CURRENT  
SETTING 2  
CURRENT  
SETTING 1  
CLK  
DATA  
LE  
24-BIT INPUT  
REGISTER  
FUNCTION  
LATCH  
CPI6 CPI5 CPI4  
HIGH Z  
CPI3 CPI2 CPI1  
22  
A, B COUNTER  
LATCH  
FROM  
SD  
OUT  
19  
AV  
FUNCTION  
LATCH  
DD  
MUXOUT  
MUX  
13  
13-BIT  
N = BP + A  
SD  
OUT  
B COUNTER  
LOAD  
RF  
RF  
A
B
PRESCALER  
P/P + 1  
IN  
IN  
LOAD  
M3 M2 M1  
6-BIT  
A COUNTER  
ADF4108  
6
CE  
AGND DGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 

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