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ADF4107BRU-REEL7 PDF预览

ADF4107BRU-REEL7

更新时间： 2024-02-14 22:45:10
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管信息通信管理
页数 文件大小 规格书
20页 752K
描述
PLL Frequency Synthesizer

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ADF4107BRU-REEL7 技术参数

Source Url Status Check Date：2013-05-01 14:56:35.524是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：MO-153AB, TSSOP-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.4Is Samacsys：N
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240电源：3/3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：4.4 mmBase Number Matches：1

ADF4107BRU-REEL7 数据手册

 浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第2页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第3页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第4页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第5页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第6页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第7页 
PLL Frequency Synthesizer  
ADF4107  
FEATURES  
GENERAL DESCRIPTION  
7.0 GHz bandwidth  
2.7 V to 3.3 V power supply  
Separate charge pump supply (VP) allows extended tuning  
voltage in 3 V systems  
Programmable dual-modulus prescaler  
8/9, 16/17, 32/33, 64/65  
Programmable charge pump currents  
Programmable antibacklash pulsewidth  
3-wire serial interface  
Analog and digital lock detect  
Hardware and software power-down mode  
The ADF4107 frequency synthesizer can be used to implement  
local oscillators in the up-conversion and down-conversion  
sections of wireless receivers and transmitters. It consists of a  
low-noise digital PFD (phase frequency detector), a precision  
charge pump, a programmable reference divider, programmable  
A and B counters, and a dual-modulus prescaler (P/P + 1). The  
A (6-bit) and B (13-bit) counters, in conjunction with the dual-  
modulus prescaler (P/P + 1), implement an N divider  
(N = BP + A). In addition, the 14-bit reference counter  
(R counter), allows selectable REFIN frequencies at the PFD  
input. A complete PLL (phase-locked loop) can be implemented  
if the synthesizer is used with an external loop filter and VCO  
(voltage controlled oscillator). Its very high bandwidth means  
that frequency doublers can be eliminated in many high  
frequency systems, simplifying system architecture and  
reducing cost.  
APPLICATIONS  
Broadband wireless access  
Satellite systems  
Instrumentation  
Wireless LANs  
Base stations for wireless radio  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DV  
R
SET  
V
CPGND  
DD  
DD  
P
REFERENCE  
14-BIT  
PHASE  
REF  
CHARGE  
PUMP  
IN  
R COUNTER  
CP  
FREQUENCY  
DETECTOR  
14  
R COUNTER  
LATCH  
LOCK  
CURRENT  
SETTING 2  
CURRENT  
SETTING 1  
DETECT  
CLK  
DATA  
LE  
24-BIT INPUT  
REGISTER  
FUNCTION  
LATCH  
CPI6 CPI5 CPI4  
HIGH Z  
CPI3 CPI2 CPI1  
22  
A, B COUNTER  
LATCH  
FROM  
SD  
19  
OUT  
AV  
FUNCTION  
LATCH  
DD  
MUXOUT  
MUX  
13  
N = BP + A  
13-BIT  
SD  
OUT  
B COUNTER  
LOAD  
RF  
RF  
A
B
PRESCALER  
P/P + 1  
IN  
IN  
LOAD  
M3 M2 M1  
6-BIT  
A COUNTER  
ADF4107  
6
CE  
AGND DGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
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