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ADF4007BCP-REEL7 PDF预览

ADF4007BCP-REEL7

更新时间： 2024-02-12 01:42:42
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 504K
描述
High Frequency Divider/PLL Synthesizer

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ADF4007BCP-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：MO-220-VGGD-1, LFCSP-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：5A991.BHTS代码：8542.39.00.01
风险等级：5.43模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-XQCC-N20JESD-609代码：e0
长度：4 mm湿度敏感等级：3
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC20,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：240
电源：3/5 V认证状态：Not Qualified
座面最大高度：1 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：3.3 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：4 mm
Base Number Matches：1

ADF4007BCP-REEL7 数据手册

 浏览型号ADF4007BCP-REEL7的Datasheet PDF文件第2页浏览型号ADF4007BCP-REEL7的Datasheet PDF文件第3页浏览型号ADF4007BCP-REEL7的Datasheet PDF文件第4页浏览型号ADF4007BCP-REEL7的Datasheet PDF文件第5页浏览型号ADF4007BCP-REEL7的Datasheet PDF文件第6页浏览型号ADF4007BCP-REEL7的Datasheet PDF文件第7页 
High Frequency Divider/PLL Synthesizer  
ADF4007  
FEATURES  
GENERAL DESCRIPTION  
7.5 GHz bandwidth  
The ADF4007 is a high frequency divider/PLL synthesizer that  
can be used in a variety of communications applications. It can  
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.  
It consists of a low noise digital PFD (phase frequency  
detector), a precision charge pump, and a divider/prescaler. The  
divider/ prescaler value can be set by two external control pins  
to one of four values (8, 16, 32, or 64). The reference divider is  
permanently set to 2, allowing an external REFIN frequency of  
up to 240 MHz.  
Maximum PFD frequency of 120 MHz  
Divide ratios of 8, 16, 32, or 64  
2.7 V to 3.3 V power supply  
Separate charge pump supply (VP) allows  
extended tuning voltage in 3 V systems  
R
SET contol of charge pump current  
Hardware power-down mode  
APPLICATIONS  
Satellite communications  
Broadband wireless access  
CATV  
Instrumentation  
Wireless LANs  
A complete PLL (phase-locked loop) can be implemented if the  
synthesizer is used with an external loop filter and a VCO  
(voltage controlled oscillator). Its very high bandwidth means  
that frequency doublers can be eliminated in many high  
frequency systems, simplifying system architecture and  
reducing cost.  
FUNCTIONAL BLOCK DIAGRAM  
V
V
CPGND  
R
SET  
P
DD  
REFERENCE  
ADF4007  
PHASE  
FREQUENCY  
DETECTOR  
REF  
R COUNTER  
CHARGE  
PUMP  
IN  
CP  
÷ 2  
MUXOUT  
MUX  
N COUNTER  
÷ 8, ÷ 16,  
÷ 32, ÷ 64  
RF  
RF  
A
B
IN  
IN  
N2  
N1  
GND  
M2  
M1  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
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