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ADCMP580BCPZ-RL7 PDF预览

ADCMP580BCPZ-RL7

更新时间： 2024-02-29 15:22:59
品牌 Logo 应用领域
亚德诺 - ADI 比较器放大器放大器电路
页数 文件大小 规格书
16页 437K
描述
Ultrafast SiGe Voltage Comparators

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ADCMP580BCPZ-RL7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：16
Reach Compliance Code：unknown风险等级：5.39
放大器类型：COMPARATOR最大平均偏置电流 (IIB)：30 µA
最大输入失调电压：10000 µVJESD-30 代码：S-XQCC-N16
JESD-609代码：e3长度：3 mm
湿度敏感等级：3负供电电压上限：-6 V
标称负供电电压 (Vsup)：-5 V功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL标称响应时间：0.18 ns
座面最大高度：0.9 mm子类别：Comparator
供电电压上限：6 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BIPOLAR
温度等级：AUTOMOTIVE端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

ADCMP580BCPZ-RL7 数据手册

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Ultrafast SiGe  
Voltage Comparators  
ADCMP580/ADCMP581/ADCMP582  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
CCI  
180 ps propagation delay  
25 ps overdrive and slew rate dispersion  
8 GHz equivalent input rise time bandwidth  
100 ps minimum pulse width  
37 ps typical output rise/fall  
10 ps deterministic jitter (DJ)  
V
TERMINATION  
TP  
V
CCO  
V
NONINVERTING  
INPUT  
P
Q OUTPUT  
Q OUTPUT  
ADCMP580/  
ADCMP581/  
ADCMP582  
CML/ECL/  
PECL  
200 fs random jitter (RJ)  
V
INVERTING  
INPUT  
N
−2 V to +3 V input range with +5 V/−5 V supplies  
On-chip terminations at both input pins  
Resistor-programmable hysteresis  
Differential latch control  
V
EE  
V
TERMINATION  
HYS  
TN  
LE INPUT  
LE INPUT  
Power supply rejection > 70 dB  
V
EE  
Figure 1.  
APPLICATIONS  
Automatic test equipment (ATE)  
High speed instrumentation  
Pulse spectroscopy  
Medical imaging and diagnostics  
High speed line receivers  
Threshold detection  
Peak and zero-crossing detectors  
High speed trigger circuitry  
Clock and data signal restoration  
GENERAL DESCRIPTION  
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage  
comparators fabricated on the Analog Devices, Inc. proprietary  
XFCB3 Silicon Germanium (SiGe) bipolar process. The  
ADCMP580 features CML output drivers, the ADCMP581  
features reduced swing ECL (negative ECL) output drivers, and  
the ADCMP582 features reduced swing PECL (positive ECL)  
output drivers.  
The CML output stage is designed to directly drive 400 mꢀ into  
50 Ω transmission lines terminated to ground. The NECL output  
stages are designed to directly drive 400 mꢀ into 50 Ω terminated  
to −2 ꢀ. The PECL output stages are designed to directly drive  
400 mꢀ into 50 Ω terminated to ꢀCCO − 2 ꢀ. High speed latch  
and programmable hysteresis are also provided. The differential  
latch input controls are also 50 Ω terminated to an independent  
ꢀ
TT pin to interface to either CML or ECL or to PECL logic.  
All three comparators offer 180 ps propagation delay and 100 ps  
minimum pulse width for 10 Gbps operation with 200 fs random  
jitter (RJ). Overdrive and slew rate dispersion are typically less  
than 15 ps.  
The ADCMP580/ADCMP581/ADCMP582 are available in a  
16-lead LFCSP_ꢀQ.  
The 5 ꢀ power supplies enable a wide −2 ꢀ to +3 ꢀ input  
range with logic levels referenced to the CML/NECL/PECL  
outputs. The inputs have 50 Ω on-chip termination resistors  
with the optional capability to be left open (on an individual  
pin basis) for applications requiring high impedance input.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.  
 
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