ADCMP553

更新时间： 2024-01-26 05:11:42

品牌	Logo	应用领域
亚德诺 - ADI		比较器
页数	文件大小	规格书
14页	557K
描述
Single Supply High Speed PECL Comparators

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ADCMP553 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP8,.19	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.49
放大器类型：	COMPARATOR	最大平均偏置电流 (IIB)：	10 µA
25C 时的最大偏置电流 (IIB)：	5 µA	最大输入失调电压：	10000 µV
JESD-30 代码：	S-PDSO-G8	JESD-609代码：	e3
长度：	3 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出类型：	OPEN-EMITTER	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP8,.19
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
子类别：	Comparator	最大压摆率：	42 mA
供电电压上限：	6 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3 mm	Base Number Matches：	1

ADCMP553 数据手册

Single Supply High Speed PECL Comparators

Preliminary Technical Data

ADCMP551/ADCMP552/ADCMP553

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Single power supply

750 ps propagation delay input to output

100 ps propagation delay dispersion

Differential PECL compatible outputs

Differential latch control

NONINVERTING

Q OUTPUT

INPUT

ADCMP551/

ADCMP552/

ADCMP553

INVERTING

Q OUTPUT

INPUT

Internal latch pull-up resistors

Power supply rejection greater than 70 dB

750 ps minimum pulse width

LATCH ENABLE

INPUT

Equivalent input rise time bandwidth > 750 MHz

Typical output rise/fall of 500 ps

Figure 1.

Programmable Hysteresis

GENERAL DESCRIPTION

The ADCMP551/ADCMP552/ADCMP553 are single supply,

high speed comparators fabricated on Analog Devices’

proprietary XFCB process. The devices feature a 750 ps

propagation delay with less than 150 ps overdrive dispersion.

Dispersion, a measure of the difference in propagation delay

under differing overdrive conditions, is a particularly important

characteristic of high speed comparators. A separate

APPLICATIONS

Automatic test equipment

High speed instrumentation

Scope and logic analyzer front ends

Window comparators

High speed line receivers

Threshold detection

programmable hysteresis pin is available on the ADCMP552.

Peak detection

High speed triggers

Patient diagnostics

A differential input stage permits consistent propagation delay

with a common-mode range from –0.2 V to VCCI – 2.0 V.

Outputs are complementary digital signals are fully compatible

with PECL 10 K and 10 KH logic families. The outputs provide

sufficient drive current to directly drive transmission lines

terminated in 50 Ω to VCCO − 2 V. A latch input is included

and permits tracking, track-and-hold, or sample-and-hold

modes of operation. The latch input pins contain internal pull-

ups that set the latch in tracking mode when left open.

Disk drive read channel detection

Hand-held test instruments

Zero crossing detectors

Line receivers and signal restoration

Clock drivers

The ADCMP551/ADCMP552/ADCMP553 are specified over

the –40°C to +85°C industrial temperature range. The

ADCMP551 is available in a 16-lead QSOP package; the

ADCMP552 is available in a 20-lead QSOP package; and the

ADCMP553 is available in an 8-lead MSOP package.

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

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