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ADCLK950/PCBZ PDF预览

ADCLK950/PCBZ

更新时间: 2024-02-22 14:21:28
品牌 Logo 应用领域
亚德诺 - ADI 半导体时钟
页数 文件大小 规格书
12页 368K
描述
Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer

ADCLK950/PCBZ 技术参数

生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:40
Reach Compliance Code:unknown风险等级:5.76
系列:950输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N40长度:6 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:40
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE传播延迟(tpd):0.21 ns
认证状态:COMMERCIALSame Edge Skew-Max(tskwd):0.045 ns
座面最大高度:1 mm最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:NOT SPECIFIED
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:6 mm
Base Number Matches:1

ADCLK950/PCBZ 数据手册

 浏览型号ADCLK950/PCBZ的Datasheet PDF文件第2页浏览型号ADCLK950/PCBZ的Datasheet PDF文件第3页浏览型号ADCLK950/PCBZ的Datasheet PDF文件第4页浏览型号ADCLK950/PCBZ的Datasheet PDF文件第5页浏览型号ADCLK950/PCBZ的Datasheet PDF文件第6页浏览型号ADCLK950/PCBZ的Datasheet PDF文件第7页 
Two Selectable Inputs, 10 LVPECL Outputs,  
SiGe Clock Fanout Buffer  
ADCLK950  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
2 selectable differential inputs  
4.8 GHz operating frequency  
75 fs rms broadband random jitter  
On-chip input terminations  
3.3 V power supply  
LVPECL  
ADCLK950  
Q0  
Q0  
Q1  
Q1  
APPLICATIONS  
Q2  
Q2  
Low jitter clock distribution  
Clock and data signal restoration  
Level translation  
Q3  
V
0
REFERENCE  
Wireless communications  
REF  
Q3  
Wired communications  
Medical and industrial imaging  
ATE and high performance instrumentation  
Q4  
Q4  
V 0  
T
CLK0  
CLK0  
GENERAL DESCRIPTION  
Q5  
Q5  
The ADCLK950 is an ultrafast clock fanout buffer fabricated  
on the Analog Devices, Inc., proprietary XFCB3 silicon german-  
ium (SiGe) bipolar process. This device is designed for high  
speed applications requiring low jitter.  
V 1  
T
CLK1  
CLK1  
Q6  
Q6  
The device has two selectable differential inputs via the IN_SEL  
control pin. Both inputs are equipped with center tapped,  
differential, 100 Ω on-chip termination resistors. The inputs  
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),  
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A  
Q7  
Q7  
IN_SEL  
Q8  
Q8  
V
1
REFERENCE  
REF  
V
REFx pin is available for biasing ac-coupled inputs.  
Q9  
Q9  
The ADCLK950 features 10 full-swing emitter coupled logic  
(ECL) output drivers. For LVPECL (positive ECL) operation,  
bias VCC to the positive supply and VEE to ground. For ECL  
operation, bias VCC to ground and VEE to the negative supply.  
Figure 1.  
The output stages are designed to directly drive 800 mV each  
side into 50 Ω terminated to VCC − 2 V for a total differential  
output swing of 1.6 V.  
The ADCLK950 is available in a 40-lead LFCSP and specified  
for operation over the standard industrial temperature range of  
−40°C to +85°C.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 
 

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