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AD9984AKCPZ-140 PDF预览

AD9984AKCPZ-140

更新时间: 2024-02-10 23:54:05
品牌 Logo 应用领域
亚德诺 - ADI 显示器驱动程序和接口接口集成电路
页数 文件大小 规格书
44页 616K
描述
High Performance 10-Bit Display Interface

AD9984AKCPZ-140 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:64
Reach Compliance Code:unknown风险等级:5.09
Is Samacsys:N接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:S-XQCC-N64JESD-609代码:e3
长度:9 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:70 °C最低工作温度:
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:1 mm最大供电电压:1.9 V
最小供电电压:1.7 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9 mmBase Number Matches:1

AD9984AKCPZ-140 数据手册

 浏览型号AD9984AKCPZ-140的Datasheet PDF文件第2页浏览型号AD9984AKCPZ-140的Datasheet PDF文件第3页浏览型号AD9984AKCPZ-140的Datasheet PDF文件第4页浏览型号AD9984AKCPZ-140的Datasheet PDF文件第5页浏览型号AD9984AKCPZ-140的Datasheet PDF文件第6页浏览型号AD9984AKCPZ-140的Datasheet PDF文件第7页 
High Performance  
10-Bit Display Interface  
AD9984A  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
10-bit, analog-to-digital converters  
170 MSPS maximum conversion rate  
Low PLL clock jitter at 170 MSPS  
Automatic gain matching  
Automated offset adjustment  
2:1 input mux  
Power-down via dedicated pin or serial register  
4:4:4, 4:2:2, and DDR output format modes  
Variable output drive strength  
Odd/even field detection  
AD9984A  
10  
AUTO OFFSET  
AUTO GAIN  
Pr/RED  
Pr/RED  
10  
10  
10  
IN1  
IN0  
2:1  
MUX  
10-BIT  
ADC  
Cb/Cr/RED  
CLAMP  
CLAMP  
CLAMP  
PGA  
PGA  
PGA  
OUT  
10  
10  
AUTO OFFSET  
AUTO GAIN  
Y/GREEN  
Y/GREEN  
IN1  
2:1  
MUX  
10-BIT  
ADC  
Y/GREEN  
OUT  
IN0  
AUTO OFFSET  
AUTO GAIN  
External clock input  
Regenerated Hsync output  
Pb/BLUE  
Pb/BLUE  
IN1  
2:1  
MUX  
10-BIT  
ADC  
Cb/BLUE  
OUT  
IN0  
Programmable output high impedance control  
Hsyncs per Vsync counter  
Sync-on-green (SOG) pulse filter  
Pb-free package  
HSYNC1  
HSYNC0  
2:1  
MUX  
DATACK  
SOGOUT  
SYNC  
VSYNC0  
VSYNC1  
2:1  
MUX  
PROCESSING  
ODD/EVEN FIELD  
HSOUT  
PLL  
POWER  
MANAGEMENT  
APPLICATIONS  
SOGIN1  
SOGIN0  
2:1  
MUX  
VSOUT/A0  
Advanced TVs  
Plasma display panels  
LCDTV  
EXTCK/COAST  
CLAMP  
REFHI  
FILT  
VOLTAGE  
REFS  
REFLO  
SDA  
SCL  
SERIAL REGISTER  
HDTV  
RGB graphics processing  
LCD monitors and projectors  
Scan converters  
Figure 1.  
GENERAL DESCRIPTION  
The AD9984A is a complete 10-bit, 170 MSPS, monolithic  
analog interface optimized for capturing YPbPr video and RGB  
graphics signals. Its 170 MSPS encode rate capability and full  
power analog bandwidth of 300 MHz support all HDTV video  
modes up to 1080p, as well as graphics resolutions up to UXGA  
(1600 × 1200 at 60 Hz).  
sampling clock phase adjustment is provided. Output data,  
sync, and clock phase relationships are maintained.  
The auto-offset feature can be enabled to automatically restore  
the signal reference levels and calibrate out any offset differences  
between the three channels. The auto channel-to-channel gain-  
matching feature can be enabled to minimize any gain  
mismatches between the three channels.  
The AD9984A includes a 170 MHz triple ADC with an internal  
reference, a PLL, and programmable gain, offset, and clamp  
control. The user provides only a 1.8 V power supply and an  
analog input. Three-state CMOS outputs can be powered from  
1.8 V to 3.3 V.  
The AD9984A also offers full sync processing for composite sync  
and sync-on-green applications. A clamp signal is generated  
internally or can be provided by the user through the CLAMP  
input pin.  
The AD9984A on-chip PLL generates a sample clock from the  
tri-level sync (for YPbPr video) or the horizontal sync (for RGB  
graphics). Sample clock output frequencies range from 10 MHz  
to 170 MHz. With internal coast generation, the PLL maintains  
its output frequency in the absence of a sync input. A 32-step  
Fabricated in an advanced CMOS process, the AD9984A is  
provided in a space-saving, Pb-free, 80-lead low profile quad  
flat package (LQFP) or 64-lead lead frame chip scale package  
(LFCSP) and is specified over the 0°C to 70°C temperature range.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  
 

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