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AD9861BCPRL-80 PDF预览

AD9861BCPRL-80

更新时间: 2024-02-27 17:27:09
品牌 Logo 应用领域
亚德诺 - ADI 电信集成电路电信电路
页数 文件大小 规格书
52页 1619K
描述
Mixed-Signal Front-End (MxFE⑩) Baseband Transceiver for Broadband Applications

AD9861BCPRL-80 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:MO-220-VMMD, LFCSP-64
针数:64Reach Compliance Code:not_compliant
ECCN代码:5A991.B.1HTS代码:8542.31.00.01
风险等级:5.11Is Samacsys:N
JESD-30 代码:S-XQCC-N64JESD-609代码:e0
长度:9 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC64,.35SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Telecom ICs
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:9 mm
Base Number Matches:1

AD9861BCPRL-80 数据手册

 浏览型号AD9861BCPRL-80的Datasheet PDF文件第2页浏览型号AD9861BCPRL-80的Datasheet PDF文件第3页浏览型号AD9861BCPRL-80的Datasheet PDF文件第4页浏览型号AD9861BCPRL-80的Datasheet PDF文件第5页浏览型号AD9861BCPRL-80的Datasheet PDF文件第6页浏览型号AD9861BCPRL-80的Datasheet PDF文件第7页 
Mixed-Signal Front-End (MxFE) Baseband  
Transceiver for Broadband Applications  
AD9861  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Receive path includes dual 10-bit analog-to-digital  
converters with internal or external reference, 50 MSPS  
and 80 MSPS versions  
Transmit path includes dual 10-bit, 200 MSPS digital-to-  
analog converters with 1×, 2×, or 4× interpolation and  
programmable gain control  
Internal clock distribution block includes a programmable  
phase-locked loop and timing generation circuitry,  
allowing single-reference clock operation  
20-pin flexible I/O data interface allows various interleaved  
or noninterleaved data transfers in half-duplex mode and  
interleaved data transfers in full-duplex mode  
VIN+A  
ADC  
ADC  
DATA  
MUX  
AND  
Rx DATA  
VIN–A  
VIN+B  
LATCH  
VIN–B  
I/O  
INTERFACE  
CONTROL  
I/O  
INTERFACE  
CONFIGURATION  
BLOCK  
FLEXIBLE  
I/O BUS  
[0:19]  
LOW-PASS  
INTERPOLATION  
FILTER  
IOUT+A  
DATA  
LATCH  
AND  
DAC  
DAC  
IOUT–A  
IOUT+B  
Tx DATA  
DEMUX  
IOUT–B  
AUX  
ADC  
Configurable through register programmability or  
optionally limited programmability through mode pins  
AUX  
DAC  
Independent Rx and Tx power-down control pins  
64-lead LFCSP package (9 mm × 9 mm footprint)  
3 configurable auxiliary converter pins  
ADC CLOCK  
CLKIN  
AUX  
DAC  
DAC CLOCK  
PLL  
APPLICATIONS  
AUX  
ADC  
Broadband access  
AD9861  
Broadband LAN  
Communications (modems)  
AUX  
DAC  
03606-0-001  
Figure 1.  
GENERAL DESCRIPTION  
of custom digital back ends or open market DSPs.  
The AD9861 is a member of the MxFE family—a group of  
integrated converters for the communications market. The  
AD9861 integrates dual 10-bit analog-to-digital converters  
(ADC) and dual 10-bit digital-to-analog converters (TxDAC®).  
Two speed grades are available, -50 and -80. The -50 is opti-  
mized for ADC sampling of 50 MSPS and less, while the -80 is  
optimized for ADC sample rates between 50 MSPS and 80 MSPS.  
The dual TxDACs operate at speeds up to 200 MHz and  
include a bypassable 2× or 4× interpolation filter. Three  
auxiliary converters are also available to provide required  
system level control voltages or to monitor system signals. The  
AD9861 is optimized for high performance, low power, small  
form factor, and to provide a cost-effective solution for the  
broadband communication market.  
In half-duplex systems, the interface supports 20-bit parallel  
transfers or 10-bit interleaved transfers. In full-duplex systems,  
the interface supports an interleaved 10-bit ADC bus and an  
interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin  
count and, therefore, reduces the required package size on the  
AD9861 and the device to which it connects.  
The AD9861 can use either mode pins or a serial program-  
mable interface (SPI) to configure the interface bus, operate the  
ADC in a low power mode, configure the TxDAC interpolation  
rate, and control ADC and TxDAC power-down. The SPI  
provides more programmable options for both the TxDAC path  
(for example, coarse and fine gain control and offset control for  
channel matching) and the ADC path (for example, the internal  
duty cycle stabilizer, and twos complement data format).  
The AD9861 uses a single input clock pin (CLKIN) to generate  
all system clocks. The ADC and TxDAC clocks are generated  
within a timing generation block that provides user programma-  
ble options such as divide circuits, PLL multipliers, and switches.  
The AD9861 is packaged in a 64-lead LFCSP (low profile, fine  
pitched, chip scale package). The 64-lead LFCSP footprint is  
only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into  
tightly spaced applications such as PCMCIA cards  
A flexible, bidirectional 20-bit I/O bus accommodates a variety  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  

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