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AD9755AST PDF预览

AD9755AST

更新时间: 2024-02-26 08:31:25
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
26页 900K
描述
12-Bit, 300 MSPS High-Speed TxDAC+?? D/A Converter

AD9755AST 数据手册

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12-Bit, 300 MSPS  
High-Speed TxDAC+® D/A Converter  
a
AD9753*  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
12-Bit Dual Muxed Port DAC  
300 MSPS Output Update Rate  
Excellent SFDR and IMD Performance  
SFDR to Nyquist @ 25 MHz Output: 69 dB  
Internal Clock Doubling PLL  
Differential or Single-Ended Clock Input  
On-Chip 1.2 V Reference  
DVDD  
LATCH  
LATCH  
DCOM  
AVDD  
ACOM  
PORT1  
PORT2  
I
I
OUTA  
OUTB  
MUX  
DAC  
Single 3.3 V Supply Operation  
Power Dissipation: 155 mW @ 3.3 V  
48-Lead LQFP  
CLK+  
CLK–  
CLKVDD  
PLLVDD  
CLKCOM  
REFIO  
FSADJ  
PLL  
CLOCK  
MULTIPLIER  
REFERENCE  
AD9753  
APPLICATIONS  
Communications: LMDS, LMCS, MMDS  
Base Stations  
RESET LPF DIV0 DIV1 PLLLOCK  
Digital Synthesis  
QAM and OFDM  
The DAC utilizes a segmented current source architecture com-  
bined with a proprietary switching technique to reduce glitch  
energy and to maximize dynamic accuracy. Differential current  
outputs support single-ended or differential applications. The  
differential outputs each provide a nominal full-scale current  
from 2 mA to 20 mA.  
PRODUCT DESCRIPTION  
The AD9753 is a dual, muxed port, ultrahigh-speed, single-  
channel, 12-bit CMOS DAC. It integrates a high-quality 12-bit  
TxDAC+ core, a voltage reference, and digital interface circuitry  
into a small 48-lead LQFP package. The AD9753 offers excep-  
tional ac and dc performance while supporting update rates up  
to 300 MSPS.  
The AD9753 is manufactured on an advanced low cost 0.35 µm  
CMOS process. It operates from a single supply of 3.1 V to 3.5 V  
and consumes 155 mW of power.  
The AD9753 has been optimized for ultrahigh-speed applica-  
tions up to 300 MSPS where data rates exceed those possible on  
a single data interface port DAC. The digital interface consists  
of two buffered latches as well as control logic. These latches  
can be time multiplexed to the high-speed DAC in several ways.  
This PLL drives the DAC latch at twice the speed of the exter-  
nally applied clock and is able to interleave the data from the  
two input channels. The resulting output data rate is twice that  
of the two input channels. With the PLL disabled, an external  
2× clock may be supplied and divided by two internally.  
PRODUCT HIGHLIGHTS  
1. The AD9753 is a member of a pin-compatible family of high-  
speed TxDAC+s providing 10-, 12-, and 14-bit resolution.  
2. Ultrahigh-Speed 300 MSPS Conversion Rate.  
3. Dual 12-Bit Latched, Multiplexed Input Ports. The AD9753  
features a flexible digital interface allowing high-speed data  
conversion through either a single or dual port input.  
The CLK inputs (CLK+/CLK–) can be driven either differen-  
tially or single-endedly, with a signal swing as low as 1 V p-p.  
4. Low Power. Complete CMOS DAC function operates on  
155 mW from a 3.1 V to 3.5 V single supply. The DAC full-  
scale current can be reduced for lower power operation.  
5. On-Chip Voltage Reference. The AD9753 includes a 1.20 V  
temperature-compensated bandgap voltage reference.  
TxDAC+ is a registered trademark of Analog Devices, Inc.  
*Protected by U.S. Patent numbers 5450084, 5568145, 5689257 and 5703519.  
Other patents pending.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  

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