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AD9575-EVALZ-LVD PDF预览

AD9575-EVALZ-LVD

更新时间: 2024-01-24 10:31:07
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
16页 306K
描述
Network Clock Generator, Two Outputs

AD9575-EVALZ-LVD 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:unknown风险等级:5.78
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm湿度敏感等级:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:312.5 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):225主时钟/晶体标称频率:25.78 MHz
认证状态:COMMERCIAL座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

AD9575-EVALZ-LVD 数据手册

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Network Clock Generator, Two Outputs  
AD9575  
FEATURES  
GENERAL DESCRIPTION  
Fully integrated VCO/PLL core  
0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz  
The AD9575 provides a highly integrated, dual output clock  
generator function including an on-chip PLL core that is  
0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz  
0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz  
0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz  
Input crystal frequency of 19.44 MHz, 25 MHz, or  
25.78125 MHz  
optimized for network clocking. The integer-N PLL design is  
based on the Analog Devices, Inc., proven portfolio of high  
performance, low jitter frequency synthesizers to maximize line  
card performance. Other applications with demanding phase  
noise and jitter requirements also benefit from this part.  
Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,  
100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,  
159.375 MHz, 161.13 MHz, and 312.5 MHz outputs  
LVDS/LVPECL/LVCMOS output format  
The PLL section consists of a low noise phase frequency detector  
(PFD), a precision charge pump, a low phase noise voltage  
controlled oscillator (VCO), and pin selectable feedback and  
output dividers.  
Integrated loop filter  
By connecting an external crystal, popular network output  
frequencies can be locked to the input reference. The output  
divider and feedback divider ratios are pin programmable for the  
required output rates. No external loop filter components are  
required, thus conserving valuable design time and board space.  
Space saving 4.4 mm × 5.0 mm TSSOP  
100 mW power dissipation (LVDS output)  
120 mW power dissipation (LVPECL output)  
3.3 V operation  
APPLICATIONS  
The AD9575 is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP  
and can be operated from a single 3.3 V supply. The temperature  
range is −40°C to +85°C.  
GbE/FC/SONET line cards, switches, and routers  
CPU/PCI-e applications  
Low jitter, low phase noise clock generation  
FUNCTIONAL BLOCK DIAGRAM  
VDD × 5  
LVDS OR  
LVPECL  
LDO  
VCO  
100MHz  
TO 312.5MHz  
XTAL  
OSC  
LVCMOS  
33.33MHz/  
62.5MHz/SEL1  
SEL  
AD9575  
GND × 5  
SEL0  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 
 
 

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