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AD9572ACPZPEC

更新时间: 2024-01-26 06:32:27
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器光纤以太网
页数 文件大小 规格书
20页 410K
描述
Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

AD9572ACPZPEC 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC40,.24SQ,20针数:40
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.25
Samacsys Description:Fiber Channel/Ethernet Clock Generator IC 7 Clock OutputsJESD-30 代码:S-XQCC-N40
JESD-609代码:e3长度:6 mm
湿度敏感等级:1端子数量:40
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:156.25 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC40,.24SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:0.8 mm子类别:Clock Generators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:6 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER

AD9572ACPZPEC 数据手册

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Fiber Channel/Ethernet Clock Generator IC,  
PLL Core, Dividers, 7 Clock Outputs  
AD9572  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
REFSEL  
Fully integrated dual VCO/PLL cores  
167 fs rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz  
178 fs rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz  
418 fs rms jitter from 12 kHz to 20 MHz at 125 MHz  
Input crystal or clock frequency of 25 MHz  
Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,  
100 MHz, 125 MHz  
Choice of LVPECL or LVDS output format  
Integrated loop filters  
Copy of reference clock output  
XTAL  
OSC  
CMOS  
1 × 25MHz  
REFCLK  
LDO  
VCO  
LVPECL  
OR LVDS  
2 × 106.25MHz  
1 × 156.25MHz  
LVPECL  
OR LVDS  
Rates configured via strapping pins  
LDO  
VCO  
LVPECL  
OR LVDS  
Space saving, 6 mm × 6 mm, 40-lead LFCSP  
0.71 W power dissipation (LVDS operation)  
1.07 W power dissipation (LVPECL operation)  
3.3 V operation  
2 × 100MHz  
OR 125MHz  
CMOS  
1 × 33.33MHz  
FORCE_LOW  
APPLICATIONS  
Fiber channel line cards, switches, and routers  
Gigabit Ethernet/PCIe support included  
Low jitter, low phase noise clock generation  
AD9572  
FREQSEL  
Figure 1.  
feedback divider and output divider. By connecting an external  
crystal or reference clock to the REFCLK pin, frequencies up to  
156.25 MHz can be locked to the input reference. Each output  
divider and feedback divider ratio is preprogrammed for the  
required output rates.  
GENERAL DESCRIPTION  
The AD9572 provides a multioutput clock generator function  
along with two on-chip PLL cores, optimized for fiber channel  
line card applications that include an Ethernet interface. The  
integer-N PLL design is based on the Analog Devices, Inc.,  
proven portfolio of high performance, low jitter frequency  
synthesizers to maximize network performance. Other applica-  
tions with demanding phase noise and jitter requirements also  
benefit from this part.  
A second PLL also operates as an integer-N synthesizer and  
drives two LVPECL or LVDS output buffers for 106.25 MHz  
operation. No external loop filter components are required, thus  
conserving valuable design time and board space.  
The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame  
chip scale package (LFCSP) and can be operated from a single  
3.3 V supply. The temperature range is −40°C to +85°C.  
The PLL section consists of a low noise phase frequency  
detector (PFD), a precision charge pump (CP), a low phase  
noise voltage controlled oscillator (VCO), and a preprogrammed  
CPU  
ISLAND  
10G SFP+  
1 × 156.25MHz  
2 × 106.25MHz  
16-PORT FIBRE CHANNEL ASIC  
1 × 100MHz/125MHz  
AD9572  
1 × 25MHz  
1 × 33.33MHz  
QUAD SFP QUAD SFP QUAD SFP QUAD SFP  
PHY  
PHY  
PHY  
PHY  
Figure 2. Typical Application  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 

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