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AD9523-1BCPZ PDF预览

AD9523-1BCPZ

更新时间: 2024-01-16 01:54:21
品牌 Logo 应用领域
亚德诺 - ADI 晶体时钟发生器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
60页 840K
描述
Low Jitter Clock Generator

AD9523-1BCPZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:72
Reach Compliance Code:unknown风险等级:5.78
Is Samacsys:NJESD-30 代码:S-XQCC-N72
JESD-609代码:e3长度:10 mm
湿度敏感等级:NOT APPLICABLE端子数量:72
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:1000 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
主时钟/晶体标称频率:400 MHz座面最大高度:1 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

AD9523-1BCPZ 数据手册

 浏览型号AD9523-1BCPZ的Datasheet PDF文件第2页浏览型号AD9523-1BCPZ的Datasheet PDF文件第3页浏览型号AD9523-1BCPZ的Datasheet PDF文件第4页浏览型号AD9523-1BCPZ的Datasheet PDF文件第5页浏览型号AD9523-1BCPZ的Datasheet PDF文件第6页浏览型号AD9523-1BCPZ的Datasheet PDF文件第7页 
Low Jitter Clock Generator with  
14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs  
AD9523-1  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Output frequency: <1 MHz to 1 GHz  
OSC_IN, OSC_IN  
Start-up frequency accuracy: < 100 ppm (determined by  
VCXO reference accuracy)  
Zero delay operation  
Input-to-output edge timing: <150 ps  
Dual VCO dividers  
OUT0,  
OUT0  
AD9523-1  
REFA,  
REFA  
OUT3,  
OUT3  
DIVIDE-BY-  
REFB,  
REFB  
8 OUTPUTS  
PLL1  
PLL2  
3, 4, 5  
OUT10,  
OUT10  
REF_TEST  
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS  
14 dedicated output dividers with jitter-free adjustable delay  
Adjustable delay: 63 resolution steps of ½ period of VCO  
output divider  
OUT13,  
OUT13  
OUT4,  
OUT4  
SCLK/SCL  
SDIO/SDA  
CONTROL  
INTERFACE  
DIVIDE-BY-  
3, 4, 5  
2
(SPI AND I C)  
6 OUTPUTS  
SDO  
Output-to-output skew: <50 ps  
OUT9,  
OUT9  
ZERO  
DELAY  
Duty cycle correction for odd divider settings  
Automatic synchronization of all outputs on power-up  
Absolute output jitter: <150 fs at 122.88 MHz  
Integration range: 12 kHz to 20 MHz  
Broadband timing jitter: 124 fs  
14-CLOCK  
DISTRIBUTION  
EEPROM  
ZD_IN, ZD_IN  
Figure 1.  
Digital lock detect  
Nonvolatile EEPROM stores configuration settings  
SPI- and I²C-compatible serial control port  
Dual PLL architecture  
PLL1  
GENERAL DESCRIPTION  
Low bandwidth for reference input clock cleanup with  
external VCXO  
The AD9523-1 provides a low power, multi-output, clock  
distribution function with low jitter performance, along with an  
on-chip PLL and VCO with two VCO dividers. The on-chip VCO  
tunes from 2.94 GHz to 3.1 GHz.  
Phase detector rate of 300 kHz to 75 MHz  
Redundant reference inputs  
Auto and manual reference switchover modes  
Revertive and nonrevertive switching  
Loss of reference detection with holdover mode  
Low noise LVCMOS output from VCXO used for RF/IF  
synthesizers  
The AD9523-1 is defined to support the clock requirements for  
long term evolution (LTE) and multicarrier GSM base station  
designs. It relies on an external VCXO to provide the reference  
jitter cleanup to achieve the restrictive low phase noise require-  
ments necessary for acceptable data converter SNR performance.  
PLL2  
Phase detector rate of up to 250 MHz  
Integrated low noise VCO  
The input receivers, oscillator, and zero delay receiver provide  
both single-ended and differential operation. When connected  
to a recovered system reference clock and a VCXO, the device  
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,  
and one dedicated buffered output from the input PLL (PLL1).  
The frequency and phase of one clock output relative to another  
clock output can be varied by means of a divider phase select  
function that serves as a jitter-free, coarse timing adjustment  
in increments that are equal to half the period of the signal  
coming out of the VCO.  
APPLICATIONS  
LTE and multicarrier GSM base stations  
Wireless and broadband infrastructure  
Medical instrumentation  
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs  
Low jitter, low phase noise clock distribution  
Clock generation and translation for SONET, 10Ge, 10G FC,  
and other 10 Gbps protocols  
An in-package EEPROM can be programmed through the serial  
interface to store user-defined register settings for power-up  
and chip reset.  
Forward error correction (G.710)  
High performance wireless transceivers  
ATE and high performance instrumentation  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.  
 

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