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AD9522-2BCPZ-REEL7 PDF预览

AD9522-2BCPZ-REEL7

更新时间: 2024-01-20 10:51:34
品牌 Logo 应用领域
亚德诺 - ADI 晶体时钟发生器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
84页 1659K
描述
12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

AD9522-2BCPZ-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC64,.35SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.31
Samacsys Confidence:Samacsys Status:Released
Schematic Symbol:https://componentsearchengine.com/symbol.php?partID=578861PCB Footprint:https://componentsearchengine.com/footprint.php?partID=578861
Samacsys PartID:578861Samacsys Image:https://componentsearchengine.com/Images/9/AD9522-2BCPZ-REEL7.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/AD9522-2BCPZ-REEL7.jpgSamacsys Pin Count:65
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Other
Samacsys Footprint Name:QFN50P900X900X100-65NSamacsys Released Date:2017-01-11 11:21:59
Is Samacsys:NJESD-30 代码:S-XQCC-N64
JESD-609代码:e3长度:9 mm
湿度敏感等级:3端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:250 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC64,.35SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3/5 V
主时钟/晶体标称频率:250 MHz认证状态:Not Qualified
座面最大高度:1 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

AD9522-2BCPZ-REEL7 数据手册

 浏览型号AD9522-2BCPZ-REEL7的Datasheet PDF文件第2页浏览型号AD9522-2BCPZ-REEL7的Datasheet PDF文件第3页浏览型号AD9522-2BCPZ-REEL7的Datasheet PDF文件第4页浏览型号AD9522-2BCPZ-REEL7的Datasheet PDF文件第5页浏览型号AD9522-2BCPZ-REEL7的Datasheet PDF文件第6页浏览型号AD9522-2BCPZ-REEL7的Datasheet PDF文件第7页 
12 LVDS/24 CMOS Output Clock Generator  
with Integrated 2.2 GHz VCO  
AD9522-2  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
CP  
LF  
Low phase noise, phase-locked loop (PLL)  
On-chip VCO tunes from 2.02 GHz to 2.335 GHz  
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz  
1 differential or 2 single-ended reference inputs  
Accepts CMOS, LVPECL, or LVDS references to 250 MHz  
Accepts 16.62 MHz to 33.3 MHz crystal for reference input  
Optional reference clock doubler  
STATUS  
OPTIONAL  
REFIN  
REF1  
REF2  
MONITOR  
VCO  
REFIN  
CLK  
ZERO  
DELAY  
DIVIDER  
AND MUXES  
Reference monitoring capability  
Auto and manual reference switchover/holdover modes,  
with selectable revertive/nonrevertive switching  
Glitch-free switchover between references  
Automatic recovery from holdover  
Digital or analog lock detect, selectable  
Optional zero delay operation  
Twelve 800 MHz LVDS outputs divided into 4 groups  
Each group of 3 has a 1-to-32 divider with phase delay  
Additive broadband jitter as low as 242 fs rms  
Channel-to-channel skew grouped outputs < 60 ps  
Each LVDS output can be configured as 2 CMOS outputs  
(for fOUT ≤ 250 MHz)  
LVDS/  
CMOS  
OUT0  
OUT1  
OUT2  
DIV/Φ  
DIV/Φ  
DIV/Φ  
DIV/Φ  
OUT3  
OUT4  
OUT5  
OUT6  
OUT7  
OUT8  
OUT9  
OUT10  
OUT11  
2
SPI/I C CONTROL  
PORT AND  
EEPROM  
AD9522  
DIGITAL LOGIC  
Automatic synchronization of all outputs on power-up  
Manual synchronization of outputs as needed  
SPI- and I²C-compatible serial control port  
64-lead LFCSP  
Figure 1.  
The AD9522 serial interface supports both SPI and IꢀC® ports.  
An in-package EEPROM can be programmed through the  
serial interface and store user-defined register settings for  
power-up and chip reset.  
Nonvolatile EEPROM stores configuration settings  
APPLICATIONS  
The AD9522 features 12 LVDS outputs in four groups. Any of  
the 800 MHz LVDS outputs can be reconfigured as two  
250 MHz CMOS outputs.  
Low jitter, low phase noise clock distribution  
Clock generation and translation for SONET, 10Ge, 10G FC,  
and other 10 Gbps protocols  
Each group of outputs has a divider that allows both the divide  
ratio (from 1 to 32) and the phase (coarse delay) to be set.  
Forward error correction (G.710)  
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs  
High performance wireless transceivers  
ATE and high performance instrumentation  
Broadband infrastructures  
The AD9522 is available in a 64-lead LFCSP and can be operated  
from a single 3.3 V supply. The external VCO can have an  
operating voltage up to 5.5 V.  
The AD9522 is specified for operation over the standard industrial  
range of −40°C to +85°C.  
GENERAL DESCRIPTION  
The AD9522-21 provides a multioutput clock distribution  
function with subpicosecond jitter performance, along with an  
on-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHz  
to 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz  
can also be used.  
The AD9520-2 is an equivalent part to the AD9522-2 featuring  
LVPECL/CMOS drivers instead of LVDS/CMOS drivers.  
1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-2 is used, it is referring to that specific  
member of the AD9522 family.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
 
 

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