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AD9514

更新时间: 2024-01-19 21:12:42
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
28页 637K
描述
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

AD9514 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:unknown风险等级:5.76
系列:9513输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:3最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):1.8 ns认证状态:COMMERCIAL
Same Edge Skew-Max(tskwd):0.3 ns座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
最小 fmax:800 MHzBase Number Matches:1

AD9514 数据手册

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1.6 GHz Clock Distribution IC,  
Dividers, Delay Adjust, Three Outputs  
AD9514  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
1.6 GHz differential clock input  
RSET  
VS  
GND  
3 programmable dividers  
Divide-by in range from1 to 32  
AD9514  
LVPECL  
OUT0  
Phase select for coarse delay adjust  
2 independent 1.6 GHz LVPECL clock outputs  
Additive broadband output jitter 225 fs rms  
1 independent 800 MHz/250 MHz LVDS/CMOS clock output  
Additive broadband output jitter 300 fs rms/290 fs rms  
Time delays up to 10 ns  
/1. . . /32  
OUT0B  
LVPECL  
CLK  
OUT1  
/1. . . /32  
/1. . . /32  
CLKB  
OUT1B  
LVDS/CMOS  
Device configured with 4-level logic pins  
Space-saving, 32-lead LFCSP  
OUT2  
Δt  
SYNCB  
OUT2B  
APPLICATIONS  
Low jitter, low phase noise clock distribution  
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs  
High performance wireless transceivers  
High performance instrumentation  
Broadband infrastructure  
SETUP LOGIC  
VREF  
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0  
Figure 1.  
ATE  
GENERAL DESCRIPTION  
The AD9514 features a multi-output clock distribution IC in a  
design that emphasizes low jitter and phase noise to maximize  
data converter performance. Other applications with demanding  
phase noise and jitter requirements also benefit from this part.  
The LVDS/CMOS output features a delay element with three  
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each  
with 16 steps of fine adjustment.  
The AD9514 does not require an external controller for  
operation or setup. The device is programmed by means of  
11 pins (S0 to S10) using 4-level logic. The programming pins  
are internally biased to ⅓ VS. The VREF pin provides a level of  
⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.  
There are three independent clock outputs. Two of the outputs  
are LVPECL, and the third output can be set to either LVDS or  
CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the  
third output operates to 800 MHz in LVDS mode and to  
250 MHz in CMOS mode.  
The AD9514 is ideally suited for data converter clocking  
applications where maximum converter performance is  
achieved by encode signals with subpicosecond jitter.  
Each output has a programmable divider that can be set to  
divide by a selected set of integers ranging from 1 to 32. The  
phase of one clock output relative to another clock output can  
be set by means of a divider phase select function that serves as  
a coarse timing adjustment.  
The AD9514 is available in a 32-lead LFCSP and operates from  
a single 3.3 V supply. The temperature range is −40°C to +85°C.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  
 

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