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AD8330ACPZ-R7 PDF预览

AD8330ACPZ-R7

更新时间: 2024-01-09 10:37:29
品牌 Logo 应用领域
亚德诺 - ADI 消费电路商用集成电路放大器PC
页数 文件大小 规格书
32页 751K
描述
Low Cost DC to 150 MHz Variable Gain Amplifier

AD8330ACPZ-R7 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:0.59
Samacsys Confidence:Samacsys Status:Released
Schematic Symbol:https://componentsearchengine.com/symbol.php?partID=577524PCB Footprint:https://componentsearchengine.com/footprint.php?partID=577524
Samacsys PartID:577524Samacsys Image:https://componentsearchengine.com/Images/9/AD8330ACPZ-R7.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/AD8330ACPZ-R7.jpgSamacsys Pin Count:17
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Other
Samacsys Footprint Name:QFN50P300X300X90-17NSamacsys Released Date:2017-01-10 13:33:33
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-XQCC-N16JESD-609代码:e3
长度:3 mm湿度敏感等级:3
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2.7 V表面贴装:YES
技术:BIPOLAR温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:3 mm
Base Number Matches:1

AD8330ACPZ-R7 数据手册

 浏览型号AD8330ACPZ-R7的Datasheet PDF文件第2页浏览型号AD8330ACPZ-R7的Datasheet PDF文件第3页浏览型号AD8330ACPZ-R7的Datasheet PDF文件第4页浏览型号AD8330ACPZ-R7的Datasheet PDF文件第5页浏览型号AD8330ACPZ-R7的Datasheet PDF文件第6页浏览型号AD8330ACPZ-R7的Datasheet PDF文件第7页 
Low Cost DC to 150 MHz  
Variable Gain Amplifier  
AD8330  
FEATURES  
Fully differential signal path and also used  
with single-sided signals  
FUNCTIONAL BLOCK DIAGRAM  
16  
15  
14  
13  
ENBL  
OFST  
VPOS  
CNTR  
Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs  
Differential RIN = 1 kΩ; ROUT (each output) 75 Ω  
Automatic offset compensation (optional)  
Linear-in-dB and linear-in-magnitude gain modes  
0 dB to 50 dB, for 0 V < VDBS < 1.5 V (30 mV/dB)  
Inverted gain mode: 50 dB to 0 dB at −30 mV/dB  
×0.03 to ×10 nominal gain for 15 mV < VMAG < 5 V  
Constant bandwidth: 150 MHz at all gains  
Low noise: 5 nV/√Hz typical at maximum gain  
Low distortion: ≤−62 dBc typical  
Low power: 20 mA typical at VS of 2.7 V to 6 V  
Available in a space-saving, 3 mm × 3 mm LFCSP package  
1
2
3
4
VPSI  
VPSO 12  
CM AND  
OFFSET  
BIAS AND V  
REF  
CONTROL  
OPHI  
11  
INHI  
OUTPUT  
STAGES  
VGA CORE  
OPLO  
10  
INLO  
MODE  
VDBS  
CMOP  
VMAG  
9
OUTPUT  
CONTROL  
GAIN INTERFACE  
CMGN  
COMM  
5
6
7
8
Figure 1.  
APPLICATIONS  
Pre-ADC signal conditioning  
75 Ω cable driving adjust  
AGC amplifiers  
Using VMAG, the basic 0 dB to 50 dB range can be repositioned  
to any value from ±0 dB higher (that is, ±0 dB to 70 dB) to at least  
30 dB lower (that is, –30 dB to +±0 dB) to suit the application,  
thereby providing an unprecedented gain range of over 100 dB.  
A unique aspect of the AD8330 is that its bandwidth and pulse  
response are essentially constant for all gains, over both the basic  
50 dB linear-in-dB range, but also when using the linear-in-  
magnitude function. The exceptional stability of the HF response  
over the gain range is of particular value in those VGA applications  
where it is essential to maintain accurate gain law-conformance at  
high frequencies.  
GENERAL DESCRIPTION  
The AD83301 is a wideband variable gain amplifier for applications  
requiring a fully differential signal path, low noise, well-defined  
gain, and moderately low distortion, from dc to 150 MHz. The  
input pins can also be driven from a single-ended source. The  
peak differential input is ±± V, allowing sine wave operation at  
1 V rms with generous headroom. The output pins can drive  
single-sided loads essentially rail-to-rail. The differential output  
resistance is 150 Ω. The output swing is a linear function of the  
voltage applied to the VMAG pin that internally defaults to 0.5 V  
providing a peak output of ±± V. This can be raised to 10 V p-p,  
limited by the supply voltage.  
An external capacitor at Pin OFST sets the high-pass corner of  
an offset reduction loop, whose frequency can be as low as 5 Hz.  
When this pin is grounded, the signal path becomes dc-coupled.  
When used to drive an ADC, an external common-mode control  
voltage at Pin CNTR can be driven to within 0.5 V of either ground  
or VS to accommodate a wide variety of requirements. By default,  
the two outputs are positioned at the midpoint of the supply, VS/±.  
Other features, such as two levels of power-down (fully off and a  
hibernate mode), further extend the practical value of this excep-  
tionally versatile VGA.  
The basic gain function is linear-in-dB, controlled by the voltage  
applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for  
control voltages between 0 V and 1.5 V—a slope of 30 mV dB.  
The gain linearity is typically within ±0.1 dB. By changing the  
logic level on Pin MODE, the gain decreases over the same range,  
with an opposite slope. A second gain control port is provided at  
the VMAG pin and allows the user to vary the numeric gain from  
a factor of 0.03 to 10. All the parameters of the AD8330 have low  
sensitivities to temperature and supply voltages.  
The AD8330 is available in 16-lead LFCSP and 16-lead QSOP  
packages and is specified for operation from −40°C to +85°C.  
1
Protected by U.S. Patent No. 5,969,657; other patents pending.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 
 

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