6.5 Gbps
Dual Buffer Mux/Demux
AD8155
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Dual 2:1 mux/1:2 demux
RECEIVE
EQUALIZATION
TRANSMIT
PRE-
EMPHASIS
Optimized for dc to 6.5 Gbps NRZ data
Per-lane P/N pair inversion for routing ease
Programmable input equalization
Compensates up to 40 inches of FR4
Loss-of-signal detection
Programmable output preemphasis up to 12 dB
Programmable output levels with squelch and disable
Accepts ac-coupled or dc-coupled differential CML inputs
50 Ω on-chip termination
EQ
EQ
Ix_A[1:0]
Ix_B[1:0]
2:1
1:2
Ox_C[1:0]
Ix_C[1:0]
Ox_A[1:0]
Ox_B[1:0]
EQ
1:2 demux supports unicast or bicast operation
Port-level loopback
Port or single lane switching
DUAL
2:1
MULTIPLEXER/
1:2
TRANSMIT
PRE-
EMPHASIS
RECEIVE
EQUALIZATION
1.8 V to 3.3 V flexible core supply
DEMULTIPLEXER
User-settable I/O supply from VCC to 1.2 V
Low power, typically 2.0 W in basic configuration
64-lead LFCSP
LB_A
LB_B
LB_C
PE_A
2
SCL
SDA
I2C_A[2:0]
I C
CONTROL
LOGIC
−40°C to +85°C operating temperature range
PE_B
PE_C
EQ_A
EQ_B
EQ_C
APPLICATIONS
CONTROL
LOGIC
Low cost redundancy switch
SEL[1:0]
BICAST
SEL4G
RESET
LOS_INT
SONET OC48/SDH16 and lower data rates
RXAUI, 4× Fibre Channel, Infiniband, and GbE over
backplane
OIF CEI 6.25 Gbps over backplane
Serial data-level shift
AD8155
Figure 1.
2-/4-/6-lane equalizers or redrivers
The main application of the AD8155 is to support redundancy
on both the backplane and the line interface sides of a serial
link. The demultiplexing path implements unicast and bicast
capability, allowing the part to support either 1 + 1 or 1:1
redundancy.
GENERAL DESCRIPTION
The AD8155 is an asynchronous, protocol-agnostic, dual-lane
2:1 switch with a total of six differential CML inputs and
six differential CML outputs. The signal path supports NRZ
signaling with data rates up to 6.5 Gbps per lane. Each lane
offers programmable receive equalization, programmable
output preemphasis, programmable output levels, and loss-of-
signal detection.
The AD8155 is also suited for testing high speed serial links
because of its ability to duplicate incoming data. In a port-
monitoring application, the AD8155 can maintain link
connectivity with a pass-through connection from Port C to
Port A while sending a duplicate copy of the data to test
equipment on Port B.
The nonblocking switch core of the AD8155 implements a
2:1 multiplexer and 1:2 demultiplexer per lane and supports
independent lane switching through the two select pins,
SEL[1:0]. Each port is a two-lane link. Every lane implements
an asynchronous path supporting dc to 6.5 Gbps NRZ data,
fully independent of other lanes. The AD8155 has low latency
and very low lane-to-lane skew.
The rich feature set of the AD8155 can be controlled either
through external toggle pins or by setting on-chip control
registers through the I2C® interface.
Rev. 0
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