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AD6620PCB PDF预览

AD6620PCB

更新时间: 2024-02-16 05:01:19
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
43页 356K
描述
65 MSPS Digital Receive Signal Processor

AD6620PCB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:QFP,针数:80
Reach Compliance Code:unknown风险等级:5.09
Is Samacsys:NJESD-30 代码:S-PQFP-G80
JESD-609代码:e3长度:14 mm
湿度敏感等级:3端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):260座面最大高度:3.4 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

AD6620PCB 数据手册

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65 MSPS Digital Receive  
Signal Processor  
a
AD6620  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
High Input Sample Rate  
65 MSPS Single Channel Real  
I
I
I
32.5 MSPS Diversity Channel Real  
32.5 MSPS Single Channel Complex  
NCO Frequency Translation  
REAL,  
DUAL REAL,  
OR COMPLEX  
INPUTS  
SERIAL OR  
PARALLEL  
OUTPUTS  
CIC  
FILTERS  
FIR  
FILTER  
OUTPUT  
FORMAT  
Q
Q
Q
Worst Spur Better than –100 dBc  
Tuning Resolution Better than 0.02 Hz  
2nd Order Cascaded Integrator Comb FIR Filter  
Linear Phase, Fixed Coefficients  
Programmable Decimation Rates: 2, 3 . . . 16  
5th Order Cascaded Integrator Comb FIR Filter  
Linear Phase, Fixed Coefficients  
Programmable Decimation Rates: 1, 2, 3 . . . 32  
Programmable Decimating RAM Coefficient FIR Filter  
Up to 130 Million Taps per Second  
256 20-Bit Programmable Coefficients  
Programmable Decimation Rates: 1, 2, 3 . . . 32  
Bidirectional Synchronization Circuitry  
Phase Aligns NCOs  
Synchronizes Data Output Clocks  
Serial or Parallel Baseband Outputs  
Pin Selectable Serial or Parallel  
Serial Works with SHARC, ADSP-21xx, Most Other  
DSPs  
16-Bit Parallel Port, Interleaved I and Q Outputs  
Two Separate Control and Configuration Ports  
Generic P Port, Serial Port  
COS  
–SIN  
P  
OR SERIAL  
CONTROL  
EXTERNAL  
SYNC  
CIRCUITRY  
COMPLEX  
NCO  
JTAG  
PORT  
both narrowband and wideband carriers to be extracted. The  
RAM-based architecture allows easy reconfiguration for multi-  
mode applications.  
The decimating filters remove unwanted signals and noise from  
the channel of interest. When the channel of interest occupies  
less bandwidth than the input signal, this rejection of out-of-  
band noise is called “processing gain.” By using large decima-  
tion factors, this “processing gain” can improve the SNR of the  
ADC by 36 dB or more. In addition, the programmable RAM  
Coefficient filter allows antialiasing, matched filtering, and  
static equalization functions to be combined in a single, cost-  
effective filter.  
3.3 V Optimized CMOS Process  
JTAG Boundary Scan  
The input port accepts a 16-bit Mantissa, a 3-bit Exponent,  
and an A/B Select pin. These allow direct interfacing with the  
AD6600, AD6640, AD9042 and most other high speed ADCs.  
Three input modes are provided: Single Channel Real, Single  
Channel Complex, and Diversity Channel Real.  
GENERAL DESCRIPTION  
The AD6620 is a digital receiver with four cascaded signal-  
processing elements: a frequency translator, two fixed-  
coefficient decimating filters, and a programmable coefficient  
decimating filter. All inputs are 3.3 V LVCMOS compatible.  
All outputs are LVCMOS and 5 V TTL compatible.  
When paired with an interleaved sampler such as the AD6600,  
the AD6620 can process two data streams in the Diversity  
Channel Real input mode. Each channel is processed with co-  
herent frequency translation and output sample clocks. In addi-  
tion, external synchronization pins are provided to facilitate  
coherent frequency translation and output sample clocks among  
several AD6620s. These features can ease the design of systems  
with diversity antennas or antenna arrays.  
As ADCs achieve higher sampling rates and dynamic range, it  
becomes increasingly attractive to accomplish the final IF stage  
of a receiver in the digital domain. Digital IF Processing is less  
expensive, easier to manufacture, more accurate, and more  
flexible than a comparable highly selective analog stage.  
The AD6620 diversity channel decimating receiver is designed  
to bridge the gap between high speed ADCs and general pur-  
pose DSPs. The high resolution NCO allows a single carrier to  
be selected from a high speed data stream. High dynamic range  
decimation filters with a wide range of decimation rates allow  
Units are packaged in an 80-lead PQFP (plastic quad flatpack)  
and specified to operate over the industrial temperature range  
(–40°C to +85°C).  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1998  

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