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AD1895AYRS PDF预览

AD1895AYRS

更新时间: 2024-02-11 16:22:21
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
24页 1104K
描述
192 kHz Stereo Asynchronous Sample Rate Converter

AD1895AYRS 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SSOP
包装说明:PLASTIC, SSOP-28针数:28
Reach Compliance Code:unknown风险等级:5.64
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:10.2 mm
湿度敏感等级:NOT SPECIFIED功能数量:1
端子数量:28最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:COMMERCIAL座面最大高度:2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

AD1895AYRS 数据手册

 浏览型号AD1895AYRS的Datasheet PDF文件第2页浏览型号AD1895AYRS的Datasheet PDF文件第3页浏览型号AD1895AYRS的Datasheet PDF文件第4页浏览型号AD1895AYRS的Datasheet PDF文件第5页浏览型号AD1895AYRS的Datasheet PDF文件第6页浏览型号AD1895AYRS的Datasheet PDF文件第7页 
192 kHz Stereo Asynchronous  
Sample Rate Converter  
a
AD1895*  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Automatically Senses Sample Frequencies  
No Programming Required  
VDD_IO VDD_CORE  
RESET  
Attenuates Sample Clock Jitter  
3.3 V to 5 V Input and 3.3 V Core Supply Voltages  
Accepts 16-/18-/20-/24-Bit Data  
Up to 192 kHz Sample Rate  
Input/Output Sample Ratios from 7.75:1 to 1:8  
Bypass Mode  
Multiple AD1895 TDM Daisy-Chain Mode  
128 dB Signal-to-Noise and Dynamic Range  
(A-Weighted, 20 Hz to 20 kHz BW)  
Up to –122 dB THD + N  
AD1895  
MUTE_IN  
FS  
OUT  
FS  
SDATA_I  
SCLK_I  
LRCLK_I  
SDATA_O  
SCLK_O  
LRCLK_O  
FIFO  
IN  
SERIAL  
INPUT  
SMODE_IN_0  
SMODE_IN_1  
SMODE_IN_2  
TDM_IN  
SERIAL  
OUTPUT  
FIR  
FILTER  
SMODE_OUT_0  
SMODE_OUT_1  
DIGITAL  
PLL  
BYPASS  
MUTE_OUT  
WLNGTH_OUT_0  
WLNGTH_OUT_1  
Linear Phase FIR Filter  
CLOCK DIVIDER  
MMODE_0  
ROM  
Hardware Controllable Soft Mute  
Supports 256 
؋
 fS, 512 
؋
 fS, or 768 
؋
 fS Master Mode  
Clock  
Flexible 3-Wire Serial Data Port with Left-Justified,  
I2S, Right-Justified (16-, 18-, 20-, 24-Bit), and TDM  
Serial Port Modes  
MCLK_IN  
MMODE_2  
MCLK_OUT  
MMODE_1  
a digital signal processor. The serial output data is dithered down  
to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is  
selected. The AD1895 sample rate converts the data from the  
serial input port to the sample rate of the serial output port. The  
sample rate at the serial input port can be asynchronous with  
respect to the output sample rate of the output serial port. The  
master clock to the AD1895, MCLK, can be asynchronous to  
both the serial input and output ports.  
Master/Slave Input and Output Modes  
28-Lead SSOP Plastic Package  
APPLICATIONS  
Home Theater Systems, Automotive Audio Systems,  
DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio  
Effects Processors  
MCLK can either be generated off-chip or on-chip by the AD1895  
master clock oscillator. Since MCLK can be asynchronous to the  
input or output serial ports, a crystal can be used to generate  
MCLK internally to reduce noise and EMI emissions on the  
board. When MCLK is synchronous to either the output or input  
serial port, the AD1895 can be configured in a master mode where  
MCLK is divided down and used to generate the left/right  
and bit clocks for the serial port that is synchronous to MCLK.  
The AD1895 supports master modes of 256 × fS, 512 × fS, and  
768 × fS for both input and output serial ports.  
PRODUCT OVERVIEW  
The AD1895 is a 24-bit, high performance, single-chip, second  
generation asynchronous sample rate converter. Based upon  
Analog Devices’ experience with its first asynchronous sample  
rate converter, the AD1890, the AD1895 offers improved perfor-  
mance and additional features. This improved performance  
includes a THD + N range of –115 dB to –122 dB depending  
on sample rate and input frequency, 128 dB (A-Weighted)  
dynamic range, 192 kHz sampling frequencies for both input and  
output sample rates, improved jitter rejection, and 1:8 upsampling  
and 7.75:1 downsampling ratios. Additional features include  
more serial formats, a bypass mode, and better interfacing to  
digital signal processors.  
Conceptually, the AD1895 interpolates the serial input data by  
a rate of 220 and samples the interpolated data stream by the  
output sample rate. In practice, a 64-tap FIR filter with 220  
polyphases, a FIFO, a digital servo loop that measures the time  
difference between input and output samples within 5 ps, and a  
digital circuit to track the sample rate ratio are used to perform  
the interpolation and output sampling. Refer to the Theory of  
Operation section. The digital servo loop and sample rate ratio  
circuit automatically track the input and output sample rates.  
(continued on page 15)  
The AD1895 has a 3-wire interface for the serial input and  
output ports that supports left-justified, I2S, and right-justified  
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output  
port supports TDM Mode for daisy-chaining multiple AD1895s to  
*Patents pending.  
REV. B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  

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