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AD15252 PDF预览

AD15252

更新时间: 2024-01-18 04:56:10
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 629K
描述
12-Bit, 65 MSPS, Dual ADC

AD15252 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:8 X 8 MM, MO-205BA, CSPBGA-64
针数:64Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
最大模拟输入电压:0.296 V最小模拟输入电压:
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-XBGA-B64
JESD-609代码:e0长度:8 mm
模拟输入通道数量:1位数:12
功能数量:2端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:UNSPECIFIED封装代码:LFBGA
封装等效代码:BGA64,8X8,20封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT APPLICABLE
电源:2.5,3.3 V认证状态:Not Qualified
采样速率:65 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.7 mm子类别:Analog to Digital Converters
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT APPLICABLE
宽度:8 mmBase Number Matches:1

AD15252 数据手册

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12-Bit, 65 MSPS, Dual ADC  
AD15252  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
AD15252  
12-bit, 65 MSPS dual ADC  
OTR_A  
Differential input with 100 Ω input impedance  
Full-scale analog input: 296 mV p-p  
170 MHz, 3 dB bandwidth  
PDWNA  
CLKA  
DATA  
BUS A  
SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN)  
SFDR (−9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN)  
435 mW per channel  
INA  
LPF  
OEB_A  
DFS  
Dual parallel output buses  
PDWNB  
CLKB  
Out-of-range indicators  
Independent clocks  
Duty cycle stabilizer  
Twos complement or offset binary data format  
DATA  
BUS B  
INB  
LPF  
OEB_B  
OTR_B  
APPLICATIONS  
Figure 1.  
Antijam GPS receivers  
Wireless and wired broadband communications  
Communications test equipment  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital  
converter (ADC). It features a differential front-end  
amplification circuit followed by a sample-and-hold amplifier  
and multistage pipeline ADC. It is designed to operate with a  
3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input  
is fully differential, ac-coupled, and terminated in 100 Ω input  
impedances. The full-scale differential signal input range is  
296 mV p-p.  
1. Dual 12-bit, 65 MSPS ADC with integrated analog signal  
conditioning optimized for antijam global positioning  
system receiver (AJ-GPS) applications.  
2. Operates from a single 3.3 V power supply and features a  
separate digital output driver supply to accommodate 2.5 V  
and 3.3 V logic families.  
3. Packaged in a space-saving 8 mm × 8 mm chip scale  
package ball grid array (CSP_BGA) and is specified over  
the industrial temperature range (–40°C to +85°C).  
Two parallel, 12-bit digital output buses provide data flow from  
the ADCs. The digital output data is presented in either straight  
binary or twos complement format. Out-of-range (OTR) signals  
indicate an overflow condition, which can be used with the  
most significant bit to determine low or high overflow. Dual  
single-ended clock inputs control all internal conversion cycles.  
A duty cycle stabilizer allows wide variations in the clock duty  
cycle while maintaining excellent performance. The AD15252 is  
optimized for applications in antijam global positioning  
receivers and is well suited for communications applications.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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