®
Quad-SHARC
a
DSP Multiprocessor Family
AD14060/AD14060L
FUNCTIO NAL BLO CK D IAGRAM
PERFORMANCE FEATURES
ADSP-21060 Core Processor (. . . ؋
4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigaw ords Addressable Off-Module Mem ory
Tw elve 40 Mbyte/ s Link Ports (Three per SHARC)
Four 40 Mbit/ s Independent Serial Ports (One from
Each SHARC)
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
CPA
SPORT 1
CPA
SPORT 1
TDI
SHARC_A
(ID = 1)
2-0
SHARC_B
(ID = 2)
2-0
One 40 Mbit/ s Com m on Serial Port
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Form ats, or
32-Bit Fixed Point Data Form at
IEEE J TAG Standard 1149.1 Test Access Port and
On-Chip Em ulation
AD14060/
AD14060L
SHARC BUS (ADDR
,
DATA
MS
, RD, WR, PAGE, ADRCLK, SW, ACK,
31-0
47-0
,
3-0
SBTS, HBR, HBG, REDY, BR , RPBA, DMAR , DMAG )
1.2
6-1
1.2
PACKAGING FEATURES
308-Lead Ceram ic Quad Flatpack (CQFP)
2.05" (52 m m ) Body Size
Cavity Up or Dow n, Configurable
Low Profile, 0.160" Height
Herm etic
SHARC_D
SHARC_C
(ID = 3)
2-0
CPA
SPORT 1
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
CPA
SPORT 1
(ID = 4)
2-0
25 Mil (0.65 m m ) Lead Pitch
29 Gram s (typical)
TDO
= 0.36؇C/ W
J C
GENERAL D ESCRIP TIO N
T he ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, each SHARC has a direct
link port connection. Externally, each SHARC has a total of
120 Mbytes/s link port bandwidth.
T he AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. T he core of
the multiprocessor is the ADSP-21060 DSP microcomputer.
T he AD14060/AD14060L modules have the highest perfor-
mance —density and lowest cost—performance ratios of any in
their class. T hey are ideal for applications requiring higher levels
of performance and/or functionality per unit area.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. T he fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
T he AD14060/AD14060L takes advantage of the built-in multi-
processing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. T he on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. T he complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
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Tel: 781/ 329-4700
Fax: 781/ 326-8703
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© Analog Devices, Inc., 1997