(Preliminary) ABX8037/38/39
38-640MHz Low Phase Noise XO
FEATURES
PACKAGE PIN ASSIGNMENT
•
•
•
Less than 0.4ps RMS (12kHz-20MHz) phase
jitter for all frequencies.
Less than 25ps peak to peak jitter for all
frequencies.
Low phase noise output (@ 1MHz frequency
offset
VDDANA
XIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
XOUT
SEL2^
OE_CTRL
DNC
GNDBUF
QBAR
∗
∗
∗
∗
∗
-144dBc/Hz for 106.25MHz
-144dBc/Hz for 156.25MHz
-144dBc/Hz for 212.5MHz
-140dBc/Hz for 312.5MHz,
-131dBC/Hz for 622.08MHz
VDDBUF
Q
GNDBUF
GNDANA
LP
LM
•
•
•
•
•
•
19MHz-40MHz crystal input.
38MHz-640MHz output.
Available in PECL, LVDS, or CMOS outputs.
Output Enable selector.
2.5V & 3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
16-pin TSSOP
3x3 QFN
12 11 10
13
9
4
8
7
6
5
XOUT
SEL2^
GNDBUF
QBAR
VDDBUF
Q
DESCRIPTION
14
15
16
ABX803X
The ABX803X is a monolithic low jitter and low
phase noise high performance clock, capable of
maintaining 0.4ps RMS phase jitter and CMOS,
LVDS or PECL outputs, covering a wide frequency
output range up to 640MHz. It allows high
OE_CTRL
DNC
1
2
3
performance and high frequency output, using a low
cost fundamental crystal of between 19-40MHz.
The frequency selector pads of ABX803X enable
output frequencies of (2, 4, 8, or 16) * FXIN. The
ABX803X is designed to address the demanding
requirements of high performance applications such
Fiber Channel, serial ATA, Ethernet, SAN, etc.
Note1: QBAR is used for single ended CMOS output.
Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCO
Divider
Charge
Output
QBAR
VCO
(FXiNx16)
Pump
XIN
Phase
Detector
XTAL
OSC
Divider
+
Loop
Q
(1,2,4,8)
XOUT
Filter
OE
Performance Tuner
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 9/1/05 Page 1