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ABB0203SC-T PDF预览

ABB0203SC-T

更新时间: 2024-01-17 05:52:50
品牌 Logo 应用领域
ABRACON 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 52K
描述
Low Skew Output Buffer

ABB0203SC-T 技术参数

生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.77Is Samacsys:N
系列:0203输入调节:STANDARD
JESD-30 代码:R-PDSO-G8长度:4.89 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):0.35 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.73 mm最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
最小 fmax:180 MHzBase Number Matches:1

ABB0203SC-T 数据手册

 浏览型号ABB0203SC-T的Datasheet PDF文件第2页浏览型号ABB0203SC-T的Datasheet PDF文件第3页浏览型号ABB0203SC-T的Datasheet PDF文件第4页浏览型号ABB0203SC-T的Datasheet PDF文件第5页浏览型号ABB0203SC-T的Datasheet PDF文件第6页 
ABB0203  
Low Skew Output Buffer  
FEATURES  
PIN CONFIGURATION  
Frequency range 75 ~ 180MHz.  
Internal phase locked loop will allow spread spec-  
trum modulation on reference clock to pass to the  
outputs (up to 100kHz SST modulation).  
Zero input - output delay.  
Less than 700 ps device - device skew.  
Less than 250 ps skew between outputs.  
Less than 150 ps cycle - cycle jitter.  
Output Enable function tri-state outputs.  
3.3V operation.  
REF  
CLK2  
CLK1  
GND  
1
2
3
4
8
7
6
5
CLKOUT  
CLK4  
VDD  
CLK3  
Available in 8-Pin 150mil SOIC.  
Remark  
If REF clock is stopped for more than 10us after it has already been  
provided to the chip, and after power-up, the output clocks will  
disappear. In that instance, a full power-up reset is required in order  
to reactivate the output clocks.  
DESCRIPTION  
The ABB0203 is a high performance, low skew, low  
jitter zero delay buffer designed to distribute high  
speed clocks and is available in an 8-pin SOIC pack-  
age. It has four outputs that are synchronized with the  
input. The synchronization is established via CLKOUT  
feed back to the input of the PLL. Since the skew be-  
tween the input and output is less than ±350 ps, the  
device acts as a zero delay buffer.  
BLOCK DIAGRAM  
REF  
CLKOUT  
CLK1  
PLL  
CLK2  
CLK3  
CLK4  
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1  

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