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9ZX21201 PDF预览

9ZX21201

更新时间: 2023-12-20 18:45:29
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
17页 515K
描述
12-output DB1200Z Compliant Buffer

9ZX21201 数据手册

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12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI  
9ZX21201  
General Description  
Features/Benefits  
The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express  
Gen3 or QPI applications. The part is backwards compatible to  
PCIe Gen1 and Gen2. A fixed external feedback maintains low drift  
for critical QPI applications. In bypass mode, the IDT9ZX21201 can  
provide outputs up to 150MHz.  
Space-saving 64-pin packages  
Fixed feedback path/ 0ps input-to-output delay  
9 Selectable SMBus Addresses/Mulitple devices can share  
the same SMBus Segment  
12 OE# pins/Hardware control of each output  
PLL or bypass mode/PLL can dejitter incoming clock  
100MHz or 133MHz PLL mode operation/supports PCIe  
and QPI applications  
Recommended Application  
12-output PCIe Gen3/ QPI differential buffer for Romley and newer  
platforms  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLL's  
Key Specifications  
Cycle-to-cycle jitter <50ps  
Output-to-output skew < 65 ps  
Input-to-output delay variation <50ps  
PCIe Gen3 phase jitter < 1.0ps RMS  
QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS  
Spread Spectrum Compatible/tracks spreading input clock  
for low EMI  
Software control of PLL Bandwidth and Bypass Settings/  
PLL can dejitter incoming clock (B Rev only)  
Output Features  
12 - 0.7V differential HCSL output pairs  
Functional Block Diagram  
OE(11:0)#  
DFB_OUT  
Z-PLL  
(SS Compatible)  
DIF(11:0)  
DIF_IN  
DIF_IN#  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
SMB_A1_tri  
Logic  
SMBDAT  
SMBCLK  
IREF  
Note: Even though the feedback is fixed, DFB_OUT still needs a  
termination network for the part to function.  
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI  
1682D - 11/19/15  
1

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