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9ZML1256 PDF预览

9ZML1256

更新时间: 2024-10-15 14:58:19
品牌 Logo 应用领域
瑞萨 - RENESAS PC
页数 文件大小 规格书
28页 778K
描述
2:12 PCIe Clock Mux Gen1-5 with SMBUS Write Protection

9ZML1256 数据手册

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9ZML1245/9ZML1255/  
9ZML1256  
2:12 Clock Multiplexer for PCIe  
Gen1–5 and UPI  
Datasheet  
Description  
Features  
12 Low-power HCSL (LP-HCSL) outputs  
The 9ZML1245/9ZML1255/9ZML1256 devices are third  
generation enhanced performance 2-input, 12-output clock  
multiplexers. Each input clock has software adjustable  
input-to-output delay when operating in Zero-Delay (ZDB) mode.  
The devices also implement an extensive set of features ensuring  
that clocks are well behaved with today's ever more complex  
power-up sequencing. The 9ZML1256 has an SMBus Write  
Lockout pin for increased device and system security.  
Integrated terminations for 85Ω (9ZXL1255/56) and 100Ω  
(9ZXL1245) systems eliminate up to 4 resistors per output pair  
Flexible Power Sequencing (FPS) configuration via SMBus  
Power Down Tolerant input (PDT); inputs: SEL_A_B#,  
SADR[1:0]_tri, OE# pins  
Input-to-output delay: 0ps default. Programmable through 360°  
2 software-configurable input-to-output delay lines  
Dedicated OE# pins support PCIe CLKREQ# function  
Up to 9 selectable SMBus addresses (9ZXL1245/55)  
SMBus Write Protect Pin (9ZXL1256)  
PCIe Clocking Architectures  
Common Clocked (CC)  
Independent Reference (IR) with and without spread spectrum  
Selectable ZDB bandwidths minimizes jitter peaking in  
cascaded ZDB topologies  
Key Specifications  
Hardware/SMBus control of ZDB and FOB modes  
Spread-spectrum compatible  
Fanout Buffer Mode additive phase jitter:  
PCIe Gen5 CC < 15fs RMS  
Up to 400MHz FOB operation  
DB2000Q additive jitter < 25fs RMS  
QPI/UPI 11.4GB/s < 40fs RMS  
IF-UPI additive jitter < 70fs RMS  
ZDB Mode phase jitter:  
100MHz ZDB mode operation  
-40°C to +85°C operating temperature range  
10 × 10 mm 72-VFQFPN package  
PCIe Gen5 CC < 24fs RMS  
Typical Applications  
QPI/UPI 11.4GB/s < 110fs RMS  
IF-UPI additive jitter < 130fs RMS  
Cycle-to-cycle jitter < 50ps  
Servers/High-performance Computing  
nVME Storage  
Networking  
Output-to-output skew < 50ps  
Accelerators  
Industrial Control  
Block Diagram  
VDDR  
VDDA  
VDD x3  
VDDIO x4  
FBOUT_NC#  
FBOUT_NC  
PLL  
DIF_INA#  
DIF_INA  
DIF_INA#  
DIF_INA  
DIF11#  
DIF11  
^SEL_A_B#  
^HIBW_BYPM-LOBW#  
^CKPWRGD_PD#  
^OE[11:0]#  
12  
outputs  
Control Logic  
SMBus  
9ZML1256  
only  
vSMB_WRTLOCK  
vSADR1_tri  
DIF0#  
DIF0  
Factory  
vSADR0_tri  
SMBCLK  
SMBDAT  
9ZML1245/55  
only  
Engine Configuration  
Resistors are integrated  
GND x7  
GNDA  
©2021 Renesas Electronics Corporation  
1
R31DS0023EU0600 May 12, 2021  

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