Datasheet > 9ZML1252E

9ZML1252E

更新时间： 2023-12-20 18:46:29

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
19页	684K
描述
2:12 Low-Power PCIe Clock Mux

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9ZML1252E 数据手册

2:12 DB1200ZL Derivative for

PCIe Gen1–4 and UPI

9ZML1232E/9ZML1252E

Datasheet

Description

Features

▪ 2 configurable low drift I2O delays up to 2.9ns; maintain

transport delay for various topologies

The 9ZML1232E/9ZML1252E are a second generation

2-input/12-output differential mux for Intel Purley and newer

platforms. It exceeds the demanding DB1200ZL performance

specifications and is backwards compatible to the 9ZML1232B. It

utilizes Low-Power HCSL-compatible outputs to reduce power

consumption and termination resistors. It is suitable for

PCI-Express Gen1–4 or QPI/UPI applications, and provides 2

configurable low-drift I2O settings, one for each input channel, to

allow I2O tuning for various topologies.

▪ LP-HCSL outputs; eliminate 24 resistors (9ZML1232E)

▪ LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors

(9ZML1252E)

▪ 9 selectable SMBus addresses; multiple devices can share

same SMBus segment

▪ Separate VDDIO for outputs; allows maximum power savings

▪ PLL or Bypass Mode; PLL can dejitter incoming clock

▪ Hardware or software-selectable PLL BW; minimizes jitter

peaking in downstream PLLs

PCIe Clocking Architectures

▪ Common Clocked (CC)

▪ Spread spectrum compatible; tracks spreading input clock for

EMI reduction

▪ Separate Reference No Spread (SRNS)

▪ Separate Reference Independent Spread (SRIS)

▪ SMBus interface; software can modify device settings without

hardware changes

Typical Applications

▪ 10 × 10 mm 72-VFQFPN package; small board footprint

Servers, Storage, Networking, SSDs

Key Specifications

Output Features

▪ 12 Low-power HCSL (LP-HCSL) output pairs (9ZML1232E)

▪ Cycle-to-cycle jitter < 50ps

▪ Output-to-output skew < 50ps

▪ Input-to-output delay: Fixed at 0 ps

▪ Input-to-output delay variation < 50ps

▪ Phase jitter: PCIe Gen4 < 0.5ps rms

▪ Phase jitter: UPI > 9.6GB/s < 0.1ps rms

▪ 12 Low-power HCSL (LP-HCSL) output pairs with 85Ω Zout

(9ZML1252E)

Block Diagram

I2O

Delay

Low Phase

Noise Z-PLL

FBOUT_NC

^SEL_A_B#

DIF_INA

(SS-

Compatible)

DIF_11

Bypass path

DIF_INB

outputs

^vHIBW_BYPM

_LOBW#

CKPWRGD_PD#

vSMB_A0_tri

vSMB_A1_tri

SMBDAT

DIF_0

NOTE: Internal series resistors are

only present on the 9ZML1252

SMBCLK

^OE(11:0)#

R31DS0025EU0500 May 12, 2021

12 3 4 5 6 7...19

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