Datasheet > 9INT31H200

9INT31H200

更新时间： 2024-10-15 14:57:27

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
9页	565K
描述
2-Output Very Low-Phase Jitter HCSL Fanout Buffer

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9INT31H200 数据手册

9INT31H200

2-Output Very Low Phase Jitter

HCSL Fanout Buffer

Datasheet

Description

Features

▪ Extremely low additive phase jitter; supports DB200H

The 9INT31H200 is a 2-output very high-performance HCSL

fanout buffer for high performance interconnect applications. It

can be used at speeds up to 350MHz and is compliant to the

DB200H specification.

requirements

▪ 3.3V operation; standard industry power supply

▪ 2 OE pins (1 for each output); easy control of clocks to CPU

sockets

Typical Applications

▪ DB200H

▪ Ethernet

▪ PCIe

▪ HCSL-compatible input; supports popular devices

▪ 1MHz to 350MHz operating frequency; covers all popular

Ethernet frequencies

▪ Space saving 3 × 3 mm 16-QFN; minimal board space

Output Features

▪ 2 HCSL differential pairs

Key Specifications

▪ Qx output-to-output skew across all outputs: 5ps (typical)

▪ RMS additive phase jitter: 64fs typical (12kHz–20MHz at

156.25MHz)

Block Diagram

vOE_[1:0]#

DIF_IN#

DIF_IN

Table 1. Power Management

DIF_IN

Running

OEx# Pin

nQx

Low¹

Running

Low¹

Running

Not Running

Notes:

1. The outputs are tristated, and the termination networks pulls them low.

Table 2. Power Connections

Pin Number

Description

VDD

8, 13

GND

Input receiver analog

DIF outputs

5, 9, 16

August 9, 2018

12 3 4 5 6 7...9

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