DATASHEET
Embedded 64-Pin Industrial Temperature
Range CK505 Compatible Clock
ICS9ERS3165
Recommended Application:
Pin Configuration
Industrial temperature CK505 compatible clock for embedded
systems
PCI0/CR#_A 1
64 SCLK
63 SDATA
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
62 REF/FSLC/TEST_SEL
61 VDDREF
60 X1
Output Features:
•
•
•
2 - CPU differential low power push-pull pairs
9 - SRC differential low power push-pull pairs
PCI3 5
PCI4/27_SEL 6
59 X2
58 GNDREF
PCI5_F/ITP_EN 7
GNDPCI 8
VDD48 9
1 - CPU/SRC selectable differential low power push-pull
pair
57 FSLB/TEST_MODE
56 CK_PWRGD/PD#
55 VDDCPU
USB48M/FSLA 10
GND48 11
•
1 - SRC/DOT selectable differential low power push-pull
pair
54 CPUT_LR0
53 CPUC_LR0
52 GNDCPU
VDDI/O96MHz 12
DOT96T/SRCT_LR0 13
DOT96C/SRCC_LR0 14
GND 15
•
•
•
•
5 - PCI, 33MHz
51 CPUT_F_LR1
50 CPUC_F_LR1
49 VDDCPU_IO
48 NC
1 - PCI_F, 33MHz free running
1 - USB, 48MHz
VDD 16
1 - REF, 14.318MHz
27FIX/LCDT/SRCT_LR1/SE1 17
27SS/LCDC/SRCC_LR1/SE2 18
GND 19
47 CPUT_ITP_LR2/SRCT8
46 CPUC_ITP_LR2/SRCC8
45 VDDSRCI/O
44 SRCT_LR7/CR#_F
43 SRCC_LR7/CR#_E
42 GNDSRC
Key Specifications:
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
VDDPLL3I/O 20
SRCT_LR2/SATACLKT 21
SRCC_LR2/SATACLKC 22
GNDSRC 23
SRC output cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 250ps
SRCT_LR3/CR#_C 24
SRCC_LR3/CR#_D 25
VDDSRCI/O 26
41 SRCT_LR6
40 SRCC_LR6
39 VDDSRC
+/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
SRCT_LR4 27
SRCC_LR4 28
38 PCI_STOP#
37 CPU_STOP#
36 VDDSRCI/O
35 SRCC_LR10
34 SRCT_LR10
33 SRCT_LR11/CR#_H
•
Does not require external pass transistor for voltage
regulator
GNDSRC 29
SRCT_LR9 30
•
Integrated 33ohm series resistors on differential outputs,
Zo=50Ω
SRCC_LR9 31
SRCC_LR11/CR#_G 32
•
Supports spread spectrum modulation, default is 0.5%
down spread
64-TSSOP
•
•
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
pin14
27_SEL
pin13
Selectable between one SRC differential push-pull pair
and two single-ended outputs
DOT96T
DOT96C
0 (B1b7=1)
1 (B1b7=0)
SRCT_LR0
SRCC_LR0
Meets PCIEX Gen2 specification on dedicated SRC
outputs. Muxed SRC outputs meet PCIEX Gen1
specification, except SRC1.
pin17
LCDT_SS
27FIX
pin18
LCDC_SS
27SS
27_SEL
0
1
•
•
Meets PCIEX <85ps cycle-tocycle jitter for SRC[11:1]
NOTE: Pin 17/18 defaults to a different spread domain
than SRC without BIOS intervention. All pin numbers are
for TSSOP package but apply to corresponding signals
on MLF as well.
Single-ended programmable slew rate control for RFI
reduction
Table 1: CPU Frequency Select Table
CPU
FSLC2
FSLB1
FSLA1
SRC
MHz
PCI
REF
MHz
USB
MHz
DOT
MHz
MHz
MHz
B0b7
B0b6
B0b5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
33.33 14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
1613C—02/08/12
1