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9DB102AGILF PDF预览

9DB102AGILF

更新时间: 2024-10-29 10:06:19
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
13页 223K
描述
PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20

9DB102AGILF 数据手册

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DATASHEET  
ICS9DB102  
Two Output Differential Buffer for PCIe Gen1 & Gen2  
Description  
Features/Benefits  
The ICS9DB102 zero-delay buffer supports PCI Express  
clocking requirements. The ICS9DB102 is driven by a differential  
SRC output pair from an ICS CK410/CK505-compliant main  
clock. It attenuates jitter on the input clock and has a selectable  
PLL Band Width to maximize performance in systems with or  
without Spread-Spectrum clocking.  
CLKREQ# pin for outputs 1 and 4/output enable for Express  
Card applications  
PLL or bypass mode/PLL can dejitter incoming clock  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLLs  
Spread Spectrum Compatible/tracks spreading input clock  
for low EMI  
SMBus Interface/unused outputs can be disabled  
Industrial temperature range available  
Output Features  
2 - 0.7V current mode differential output pairs (HCSL)  
Key Specifications  
Cycle-to-cycle jitter < 35ps  
Output-to-output skew < 25ps  
Functional Block Diagram  
CLKREQ0#  
CLKREQ1#  
PCIEX0  
PCIEX1  
CLK_INT  
SPREAD  
COMPATIBLE  
PLL  
CLK_INC  
PLL_BW  
SMBDAT  
SMBCLK  
CONTROL  
LOGIC  
IREF  
IDTTM Two Output Differential Buffer for PCIe Gen1 & Gen2  
852 REV J 01/15/10  
1

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