Datasheet > 98ULPA877A

98ULPA877A

更新时间： 2023-12-20 18:44:15

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
15页	362K
描述
1.8V Low-Power Wide-Range Frequency Clock Driver

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数据手册

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98ULPA877A 数据手册

ICS98ULPA877A

1.8V Low-Power Wide-Range Frequency Clock Driver

Pin Configuration

RecommendedApplication:

•

DDR2 Memory Modules / Zero Delay Board Fan Out

Provides complete DDR2 DIMM logic solution

ProductDescription/Features:

•

Low skew, low jitter PLL clock driver

1 to 10 differential clock distribution (SSTL_18)

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

Auto PD when input signal is at a certain logic state

SwitchingCharacteristics:

•

Period jitter:40ps (DDR2-400/533)

30ps (DDR2-667/800)

Half-period jitter: 60ps (DDR2-400/533)

50ps (DDR2-667/800)

OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)

30ps (DDR2-667/800)

CYCLE - CYCLE jitter 40ps

52-Ball BGA

Top View

CLKT1

CLKC1

CLKC2

CLKT2

CLK_INT

CLK_INC

AGND

AVDD

CLKT3

CLKC3

CLKT0

GND

VDDQ

GND

CLKC0

GND

CLKC5

GND

CLKT5

GND

VDDQ

GND

CLKC9

CLKT6

CLKC6

CLKC7

CLKT7

FB_INT

FB_INC

FB_OUTC

FB_OUTT

CLKT8

VDDQ

GND

CLKC4

GND

CLKT4

GND

CLKT9

CLKC8

Block Diagram

LD or OE⁽¹⁾

POWER

DOWN

AND

TEST

MODE

LOGIC

CLKT0

LD, OS, or OE

PLL BYPASS

CLKC0

CLKT1

AV^DD

CLKC7

CLKT7

VDDQ

CLKC1

CLKT2

V^DDQ

CLKC2

CLKT2

CLKC2

CLKT3

FB_INT

FB_INC

FBOUTC

FBOUTT

V^DDQ

CLK_INT

CLK_INC

V^DDQ

CLKC3

CLKT4

CLKC4

CLKT5

CLK_INT

CLK_INC

AGND

AV^DD

CLKC5

CLKT6

10K - 100K

PLL

V^DDQ

CLKC6

CLKT7

FBIN_INT

FBIN_INC

GND

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

NOTE:

1. The Logic Detect (LD) powers down the device

when a logic LOW is applied to both CLK_INT and

CLK_INC.

40-Pin MLF

FBOUTT

FBOUTC

1177F—12/10/09

12 3 4 5 6 7...15

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