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950508FLFT

更新时间: 2024-09-16 09:20:39
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
19页 161K
描述
Clock Generator, PDSO56

950508FLFT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SSOP, SSOP56,.4Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G56
JESD-609代码:e3湿度敏感等级:1
端子数量:56最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:2.5,3.3 V认证状态:Not Qualified
子类别:Clock Generators表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

950508FLFT 数据手册

 浏览型号950508FLFT的Datasheet PDF文件第2页浏览型号950508FLFT的Datasheet PDF文件第3页浏览型号950508FLFT的Datasheet PDF文件第4页浏览型号950508FLFT的Datasheet PDF文件第5页浏览型号950508FLFT的Datasheet PDF文件第6页浏览型号950508FLFT的Datasheet PDF文件第7页 
Integrated  
Circuit  
ICS950508  
Systems, Inc.  
Programmable Timing Control Hub™ for PII/III™  
Recommended Application:  
810/810E/815 and 815 B-Step type chipset  
Pin Configuration  
VDDREF  
X1  
X2  
GND  
GND  
3V66_0  
3V66_1  
3V66_2  
VDD3V66  
VDDPCI  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
REF0/FS41*  
VDDLAPIC  
IOAPIC  
VDDLCPU  
CPUCLK0  
CPUCLK1  
GND  
Output Features:  
2 - CPUs @ 2.5V  
13 - SDRAM @ 3.3V  
3 - 3V66 @ 3.3V  
GND  
8 - PCI @3.3V  
SDRAM0  
SDRAM1  
SDRAM2  
VDDSDR  
SDRAM3  
SDRAM4  
SDRAM5  
GND  
SDRAM6  
SDRAM7  
SDRAM_F  
VDDSDR  
GND  
24_48MHz/FS2*  
48MHZ/FS3*  
VDD48  
VDDSDR  
SDRAM8  
SDRAM9  
GND  
1 - 24/48MHz@ 3.3V  
1 - 48MHz @ 3.3V fixed  
1 - REF @3.3V, 14.318MHz  
1*FS0/PCICLK0  
1*FS1/PCICLK1  
1*SEL24_48#/PCICLK2  
GND  
PCICLK3  
PCICLK4  
PCICLK5  
VDDPCI  
PCICLK6  
PCICLK7  
GND  
Features/Benefits:  
Programmable output frequency.  
Programmable output divider ratios.  
Programmable output rise/fall time.  
Programmable output skew.  
Programmable spread percentage for EMI control.  
Watchdog timer technology to reset system  
if system malfunctions.  
Vtt_PWRGD/PD#  
SCLK  
SDATA  
VDDSDR  
SDRAM11  
SDRAM10  
GND  
Programmable watch dog safe frequency.  
Support I2C Index read/write and block read/write  
operations.  
56-Pin 300-mil SSOP  
1. These pins will have 1.5 to 2X drive strength.  
* Internal Pull-up resistor of 120K to VDD  
Uses external 14.318MHz crystal.  
Key Specifications:  
CPU Output Jitter: <250ps  
IOAPIC Output Jitter: <500ps  
48MHz, 3V66, PCI Output Jitter: <500ps  
Ref Output Jitter. <1000ps  
CPU Output Skew: <175ps  
PCI Output Skew: <500ps  
3V66 Output Skew <175ps  
For group skew timing, please refer to the  
Group Timing Relationship Table.  
Block Diagram  
PLL2  
48MHz  
24_48MHz  
/ 2  
X1  
X2  
XTAL  
OSC  
REF0  
PLL1  
Spread  
CPU  
DIVDER  
CPUCLK (1:0)  
2
Spectrum  
SDRAM  
DIVDER  
SDRAM (11:0)  
SDRAM_F  
IOAPIC  
12  
FS(4:0)  
Control  
Logic  
IOAPIC  
DIVDER  
PD#  
SEL24_48#  
Vtt_PWRGD  
SDATA  
Config.  
Reg.  
PCI  
DIVDER  
PCICLK (7:0)  
3V66 (2:0)  
8
3
SCLK  
3V66  
DIVDER  
0470E—04/06/05  

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