Datasheet > 935324452528

935324452528

更新时间： 2024-11-09 10:38:35

品牌	Logo	应用领域
恩智浦 - NXP		时钟微控制器外围集成电路
页数	文件大小	规格书
114页	909K
描述
Microcontroller

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935324452528 技术参数

生命周期：	Active	包装说明：	LQFP,
Reach Compliance Code：	unknown	风险等级：	5.78
具有ADC：	YES	地址总线宽度：
位大小：	32	最大时钟频率：	16 MHz
DMA 通道：	YES	外部数据总线宽度：
长度：	24 mm	I/O 线路数量：	149
端子数量：	176	PWM 通道：	YES
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	速度：	64 MHz
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	24 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER RISC	Base Number Matches：	1

935324452528 数据手册

NXP Semiconductors

Data Sheet: Technical Data

Document Number: MPC5607B

Rev. 9, 11/2017

MPC5607B

MPC5607B Microcontroller

Data Sheet

144 LQFP (20 mm x 20 mm)

208 MAPBGA (17 mm x 17 mm)

100 LQFP (14 mm x 14mm)

LQFP176 (24 mm x 24 mm)

Features

•

Up to 10 serial communication interface (LINFlex)

modules

Up to 6 enhanced full CAN (FlexCAN) modules with

configurable buffers

•

Single issue, 32-bit CPU core complex (e200z0h)

—

Compliant with the Power Architecture^®technology

embedded category

1 inter-integrated circuit (I²C) interface module

Up to 149 configurable general purpose pins supporting

input and output operations (package dependent)

Real-Time Counter (RTC)

Clock source from internal 128 kHz or 16 MHz oscillator

supporting autonomous wakeup with 1 ms resolution with

maximum timeout of 2 seconds

Optional support for RTC with clock source from external

32 kHz crystal oscillator, supporting wakeup with 1 sec

resolution and maximum timeout of 1 hour

Up to 8 periodic interrupt timers (PIT) with 32-bit counter

resolution

Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class Two Plus

Device/board boundary scan testing supported per Joint

Test Action Group (JTAG) of IEEE (IEEE 1149.1)

On-chip voltage regulator (VREG) for regulation of

input supply for all internal levels

—

Enhanced instruction set allowing variable length

encoding (VLE) for code size footprint reduction.

With the optional encoding of mixed 16-bit and

32-bit instructions, it is possible to achieve

significant code size footprint reduction.

•

Up to 1.5 MB on-chip code flash memory supported with

the flash memory controller

64 (4 × 16) KB on-chip data flash memory with ECC

Up to 96 KB on-chip SRAM

Memory protection unit (MPU) with 8 region descriptors

and 32-byte region granularity on certain family members

(Refer to Table 1 for details.)

Interrupt controller (INTC) capable of handling 204

selectable-priority interrupt sources

Frequency modulated phase-locked loop (FMPLL)

Crossbar switch architecture for concurrent access to

peripherals, Flash, or RAM from multiple bus masters

16-channel eDMA controller with multiple transfer

request sources using DMA multiplexer

•

Boot assist module (BAM) supports internal Flash

programming via a serial link (CAN or SCI)

Timer supports I/O channels providing a range of 16-bit

input capture, output compare, and pulse width

modulation functions (eMIOS)

•

2 analog-to-digital converters (ADC): one 10-bit and one

12-bit

Cross Trigger Unit to enable synchronization of ADC

conversions with a timer event from the eMIOS or PIT

Up to 6 serial peripheral interface (DSPI) modules

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...114

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