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935313269518

更新时间： 2024-09-27 04:08:35

品牌	Logo	应用领域
恩智浦 - NXP		微控制器
页数	文件大小	规格书
77页	1085K
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RISC Microcontroller

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935313269518 数据手册

Document Number SAC57D54H

Rev. 7, 05/2017

NXP Semiconductors

Data Sheet: Technical Data

SAC57D54H

Features

• Debug functionality

– Run-time debug control of cores and visibility of

system resources using the Debug Access Port

(DAP)

– IEEE 1149.1/ IEEE 1149.7 System JTAG Controller

(SJTAG)

– Program and Data Trace support (16-bit data width)

implemented by the ARM Trace Port Interface Unit

(TPIU) Trace capture

• ARM™ Cortex-A5, 32-bit CPU

– Supports ARMv7- ISA

– 32 KB Instruction cache, 32 KB Data cache

– NEON SIMD Media Processing Engine

– FPU supporting double precision floating point

operations

– Memory Management Unit

– GIC Interrupt Controller

– Up to 320 MHz

• Timer

– Four 8-channel Flextimer modules (FTM)

– Two 4 channel System Timer Module (STM)

– Three Software WatchDog Timers (SWT)

– One 8 channel Periodic Interrupt Timer (PIT)

– Autonomous Real Time Counter (RTC)

• ARM™ Cortex-M4, 32-bit CPU

– Supports ARMv7 - ISA

– 16 KB Instruction cache, 16 KB Data cache

– 64 KB Tightly-Coupled Memory (TCM)

– Single Precision FPU

– NVIC Interrupts Controller

• Analog

– 1.25 DMIPS per MHz integer performance

– Up to 160 MHz

– 1 x 24 channel, 12-bit analog-to-digital converter

(ADC)

– 2 analog comparators (CMP)

• I/O Processor

– ARM™ Cortex-M0+, 32-bit CPU

– Intelligent Stepper Motor Drive

• Security

– Cryptographic Services Engine (CSE)

• Memory subsystem

• Safety

– System Memory Protection Unit

– 4 MB on-chip flash supported with the flash

controller

– 1 MB on-chip SRAM with ECC

– 1.3 MB on-chip Graphics SRAM with FlexECC

– ISO26262 ASIL-B compliance

– Password and Device Security (PASS) supporting

advanced censorship and life-cycle management

– One Fault Collection and Control Unit (FCCU) to

collect faults and issue interrupts

• Supports wake-up from low power modes via the

WKPU controller

• Multiple operating modes

– Includes enhanced low power operation

• On-chip voltage regulator

• Memory interfaces

– External 3.3 V input supply

– 2 x Dual QuadSPI Serial flash controllers

– Supports SDR and DDR serial flash

– Support for 3.3 V Hyperflash (Spansion)

– DRAM controller supporting SDR and DDR2

– Option for direct, external supply of core voltage

– Low Voltage Detect (LVD) and High Voltage

Detect (HVD) on various supplies and regulators

• Clock interfaces

– 8-40 MHz external crystal (FXOSC)

– 16 MHz IRC (FIRC)

– 128 kHz IRC (SIRC)

– 32 kHz external crystal (SXOSC)

– Clock Monitor Unit (CMU)

– Frequency modulated phase-locked loop (FMPLL)

– Real Time Counter (RTC)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...77

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