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935303396023 PDF预览

935303396023

更新时间： 2024-09-17 19:33:03
品牌 Logo 应用领域
恩智浦 - NXP 放大器商用集成电路
页数 文件大小 规格书
32页 407K
描述
3.4W, 2 CHANNEL, AUDIO AMPLIFIER, PBGA9, 1.30 X 1.30 MM, 0.60 MM HEIGHT, 0.40 MM PITCH, WLCSP-9

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935303396023 技术参数

生命周期：Obsolete包装说明：VFBGA,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.33.00.01风险等级：5.83
商用集成电路类型：AUDIO AMPLIFIER谐波失真：10%
JESD-30 代码：S-PBGA-B9长度：1.25 mm
信道数量：2功能数量：1
端子数量：9最高工作温度：85 °C
最低工作温度：-40 °C标称输出功率：3.4 W
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：SQUARE封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
座面最大高度：0.6 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.4 mm端子位置：BOTTOM
宽度：1.25 mmBase Number Matches：1

935303396023 数据手册

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TFA9881  
3.4 W PDM input class-D audio amplifier  
Rev. 3 — 23 April 2013  
Product data sheet  
1. General description  
The TFA9881 is a mono, filter-free class-D audio amplifier in a 9-bump WLCSP (Wafer  
Level Chip-Size Package) with a 400 m pitch.  
The digital input interface is an over-sampled Pulse Density Modulated (PDM) bit stream.  
The TFA9881 receives audio and control settings via this interface. Dedicated silence  
patterns are used to configure the control settings of the device, such as mute, gain, Pulse  
Width Modulated (PWM) output slope, clip control and bandwidth extension (this control  
mechanism is not required if the default settings are used). The Power-down to Operating  
mode transition is triggered when a clock signal is detected.  
The device features low RF susceptibility because it has a digital input interface that is  
insensitive to clock jitter. The second order closed loop architecture used in the TFA9881  
provides excellent audio performance and high supply voltage ripple rejection.  
2. Features and benefits  
Small outline WLCSP9 package: 1.3 1.3 0.6 mm  
Wide supply voltage range (fully operational from 2.5 V to 5.5 V)  
High efficiency (90 %, 4 /20 H load) and low power dissipation  
Quiescent power:  
6.5 mW (VDDD = 1.8 V, VDDP = 3.6 V, 4 /20 H load, fclk = 2.048 MHz)  
7.8 mW (VDDD = 1.8 V, VDDP = 3.6 V, 4 /20 H load, fclk = 6.144 MHz)  
Output power:  
1.4 W into 4 at 3.6 V supply (THD = 1 %)  
2.7 W into 4 at 5.0 V supply (THD = 1 %)  
3.4 W into 4 at 5.0 V supply (THD = 10 %)  
Output noise voltage: 24 V (A-weighted)  
Signal-to-noise ratio: 103 dB (VDDP = 5 V, A-weighted)  
Fully short-circuit proof across load and to supply lines  
Current limiting to avoid audio holes  
Thermally protected  
Undervoltage and overvoltage protection  
High-pass filter for DC blocking  
Invalid data protection  
Simple two-wire interface for audio and control settings  
Left/right selection  
Three gain settings:3 dB, 0 dB and +3 dB  
PWM output slope setting for EMI reduction  
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