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935066520112

更新时间： 2024-11-09 19:36:27
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 97K
描述
IC ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SSOP-24, Bus Driver/Transceiver

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935066520112 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP,
针数：24Reach Compliance Code：unknown
风险等级：5.73系列：ABT
JESD-30 代码：R-PDSO-G24长度：8.2 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：1
功能数量：8端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
传播延迟（tpd）：7.1 ns认证状态：Not Qualified
座面最大高度：2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
Base Number Matches：1

935066520112 数据手册

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Philips Semiconductors Advanced BiCMOS Products  
Product specification  
Octal latched transceiver with dual enable,  
inverting (3-State)  
74ABT544  
FEATURES  
FUNCTIONAL DESCRIPTION  
• ESD protection exceeds 2000 V per MIL  
The ’ABT544 contains two sets of eight  
D–type latches, with separate control pins for  
each set. Using data flow from A to B as an  
example, when the A-to-B Enable (EAB)  
input and the A-to-B Latch Enable (LEAB)  
input are Low the A-to-B path is transparent.  
A subsequent Low-to-High transition of the  
LEAB signal puts the A data into the latches  
where it is stored and the B outputs no longer  
change with the A inputs. With EAB and  
OEAB both Low, the 3-State B output buffers  
are active and invert the data present at the  
outputs of the A latches.  
STD 883 Method 3015 and 200 V per  
• Combines 74ABT245 and 74ABT373 type  
Machine Model  
functions in one device  
• 8-bit octal transceiver with D-type latch  
• Back-to-back registers for storage  
DESCRIPTION  
The 74ABT544 high-performance BiCMOS  
device combines low static and dynamic  
power dissipation with high speed and high  
output drive.  
• Separate controls for data flow in each  
direction  
• Output capability: +64mA/–32mA  
• Live insertion/extraction permitted  
• Power-up 3-State  
The 74ABT544 Octal Registered Transceiver  
contains two sets of D-type latches for  
temporary storage of data flowing in either  
direction. Separate Latch Enable (LEAB,  
LEBA) and Output Enable (OEAB, OEBA)  
inputs are provided for each register to  
permit independent control of data transfer in  
either direction. The outputs are guaranteed  
to sink 64mA.  
• Power-up reset  
Control of data flow from B to A is similar, but  
using the EBA, LEBA, and OEBA inputs.  
• Latch-up protection exceeds 500mA per  
Jedec JC40.2 Std 17  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE  
ORDER CODE  
74ABT544N  
DRAWING NUMBER  
0410D  
24-pin plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
24-pin plastic SOL  
74ABT544D  
0173D  
24-pin plastic SSOP Type II  
74ABT544DB  
1641A  
PIN CONFIGURATION  
LOGIC SYMBOL  
LOGIC SYMBOL (IEEE/IEC)  
2
(AB)  
1EN3  
G1  
23  
1
LEBA  
OEBA  
A0  
1
2
3
4
5
24  
23  
22  
21  
20  
V
CC  
1C5  
2EN4  
G2  
13  
11  
14  
EBA  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
(BA)  
3
4
5
6
7
8
9
10  
2C6  
A1  
A0 A1 A2 A3 A4 A5 A6 A7  
EAB  
3
4
22  
21  
20  
19  
18  
17  
16  
15  
A2  
5D  
3
11  
23  
14  
1
6
7
8
9
19  
18  
17  
16  
A3  
5D  
EBA  
OEAB  
OEBA  
13  
2
4
A4  
5
LEAB  
LEBA  
A5  
6
A6  
B0 B1 B2 B3 B4 B5 B6 B7  
7
A7 10  
15 B7  
8
11  
14  
EAB  
LEAB  
22 21 20 19 18 17 16 15  
9
GND 12  
13 OEAB  
10  
1
June 1, 1993  
853–1610 09907  
12345678

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