Datasheet > 934055222118

934055222118

更新时间： 2024-09-24 10:02:23

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	145K
描述
TRANSISTOR 48 A, 25 V, 0.018 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, DPAK-3, FET General Purpose Power

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934055222118 数据手册

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHP50N03LT, PHB50N03LT

PHD50N03LT

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

• High thermal cycling performance

• Low thermal resistance

• Logic level compatible

V_DSS= 25 V

I_D= 48 A

_DS(ON)≤ 16 mΩ (V_GS= 10 V)

R_DS(ON)≤ 21 mΩ (V_GS= 5 V)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.

Applications:-

• High frequency computer motherboard d.c. to d.c. converters

• High current switching

The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB50N03LT is supplied in the SOT404 (D²PAK) surface mounting package.

The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404 (D²PAK)

SOT428 (DPAK)

tab

DESCRIPTION

tab

gate

drain ¹

source

1 2 3

tab drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

Drain-source voltage

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

± 15

Drain-gate voltage

Gate-source voltage (DC)

Gate-source voltage (pulse

peak value)

V_GSM

T_j≤ 150˚C

± 20

I_D

Drain current (DC)

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

180

I_DM

Drain current (pulse peak

value)

P_tot

T_j, T_stg

Total power dissipation

Operating junction and

storage temperature

T_mb= 25 ˚C

175

˚C

- 55

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

October 1999

Rev 1.800

12 3 4 5 6 7...14

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