Crystal Clock Oscillators
(+3.0V, +3.3V or +5V PROGRAMMABLE MODELS)
91SMOP
STANDARD SMD CLOCK OSCILLATORS
91SMOP
STANDARD SPECIFICATIONS
using PLL technology
Item
Specifications
91SMOP※1
Generic part number
Frequency range
Frequency stability
(-20˚C to ＋75˚C)
1.000 MHz to 200.000 MHz
91SMOP(A) : ±100 ppm
91SMOP(B) : ±50 ppm
1.000 MHz to 80.000 MHz
91SMOP(J) : ±100 ppm
91SMOP(K) : ±50 ppm
over all conditions
Operating Conditions
Operating temperature
Input voltage (VDD)
Tri-state control (Option1)
OE control voltage
-
20˚C to ＋75˚C
Actual Size
＋3.0V ±10%, ＋3.3V ±10% or ＋5V ±10%
＋3.0V & ＋3.3V models
SMI P/N
＋3.0V & ＋3.3V models
SMI P/N
91SMOP(3VJ)OE
91SMOP(3VK)OE
SMI P/N
91SMOP(5VJ)OE
91SMOP(5VK)OE
SMI P/N
91SMOP(3VJ)SB
91SMOP(3VK)SB
SMI P/N
91SMOP
7.0 0.2
V
V
IH : ＋2.2 VDD min.
IL : ＋0.5 VDD max.
＋5V models
91SMOP(3VA)OE
91SMOP(3VB)OE
SMI P/N
91SMOP(5VA)OE
91SMOP(5VB)OE
SMI P/N
91SMOP(3VA)SB
91SMOP(3VB)SB
SMI P/N
V
V
IH : ＋2.2 VDD min.
IL : ＋0.5 VDD max.
＋5V models
#4
#3
(Pin#1)/(Pin#3)
OPEN→Output
VIH→Output
VIH : ＋4.0 VDD min.
V
IH : ＋4.0 VDD min.
IL→High Impedance※2
#1
#2
V
VIL : ＋0.5 VDD max.
V
IL : ＋0.5 VDD max.
(※2) Internal crystal oscillation to continue.
Tri-state control (Option2)
Stand-by (SB) control voltage
＋3.0V & ＋3.3V models
＋3.0V & ＋3.3V models
1.4
#1
3.68
5.08
1.4
#2
V
V
IH : ＋2.2 VDD min.
IL : ＋0.5 VDD max.
＋5V models
V
V
IH : ＋2.2 VDD min.
IL : ＋0.5 VDD max.
＋5V models
(Pin#1)/(Pin#3)
OPEN→Output
VIH→Output
#4
#3
VIH : ＋4.0 VDD min.
91SMOP(5VA)SB
91SMOP(5VB)SB
V
IH : ＋4.0 VDD min.
91SMOP(5VJ)SB
91SMOP(5VK)SB
VIL→High Impedance※3
PIN
1
2
3
4
CONNECTION
"L" OPEN or "H"
VIL : ＋0.5 VDD max.
V
IL : ＋0.5 VDD max.
(※3) Internal crystal oscillation to stop.
GND
Absolute Max. Ratings
Supply voltage
Z
OUTPUT
VDD
-0.5V to ＋7.0V DC
Z : high impedance
Storage temperature
-
55˚C to ＋125˚C
OUTPUT WAVEFORM
VDD
Input current
(Pin#1=Open or VIH
＋3.0V ±10%
＋3.0V ±10%
＋5V ±10%
30 mA max.
30 mA max.
50 mA max.
20 mA max.
20 mA max.
30 mA max.
TR
TF
VOH ("1"Level)
)
90% or 80% VDD
50% VDD
by current※3(option)
20˚C to ＋75˚C)
10% or 20% VDD
OV DC
VOL ("0"Level)
Stand
Output (
-
50μA max. (VDD = ＋3.0V & Pin #1=VIL)
GND
t
-
T
Symmetry=t/T×100(%)
Symmetry
45% to 55% at 50%VDD level (1.00MHz to 80.00MHz)
40% to 60% at 50%VDD level (80.00MHz to 200.00MHz)
TEST CIRCUIT
Rise and fall times
"0" level
5 ns max. (20%VDD to 80%VDD level)
VOL : 10%VDD max. (1.00MHz to 130.00MHz)
VOL : 20%VDD max. (130.00MHz to 200.00MHz)
Test Point
VDD
A
#4
#3
VDD
OUTPUT
"1" level
VOH : 90%VDD min. (1.00MHz to 130.00MHz)
VOH : 80%VDD min. (130.00MHz to 200.00MHz)
DC Power
Supply
TRI-STATE
V
GND
#2
CL
#1
Load
15 pF max. (CMOS)
50 pF max. (CMOS)
Disable delay time
Enable delay time
100 ns max.
150 ns max.(OE models)
10 ms max.(Stand-by models)
CL : including fixture and probe capacitance.
SOLDERING PATTERN
1.8
1.8
3.28
Startup time
10 ms max.
Jitter (pSp-p)
Aging (non operating)
Reflow condition
100, 200, 250 max. (depending on frequencies)
±5 ppm max. at ＋25˚C ±3˚C for first year
＋250˚C ±10˚C for 10 seconds
＋170˚C ±10˚C for 1 to 2 minutes (preheating)
0.01μF
〜
0.1μF
5.08
PACKAGE DATA
TAPE SPECIFICATIONS
4.0 0.1
Package
Item
(※1) Final exact part number to be determined with frequency,
91SMOP
frequency stability, operating temperature and input voltage.
e.g. 91SMOP(3.3VA)SB 200.000 MHz.
(※2) Internal crystal oscillation to continue(Pin #1=VIL).
(※3) Internal crystal oscillation to be halted(Pin #1=VIL).
2.0 0.1
L
Lid
Ceramic
Ceramic
+
0.1
φ1.5
-0
Base
Sealing
Terminal
Glass
J
Tungsten (metalized)
Gold / Nickel
(surface) / (under)
Compliant
B
F
M
Terminal plating
RoHS
A
B
C
D
F
J
L
M
Reel Dia.
Qty/Reel
7.4 5.4 16.0 7.5 8.0 1.5 0.3 1.9
180 1000pcs
82
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