Datasheet > 91309MILF-T

91309MILF-T

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	106K
描述
Clock Driver

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91309MILF-T 数据手册

ICS91309I

Integrated

Circuit

Systems,Inc.

High Performance Communication Buffer

General Description

Features

The ICS91309I is a high performance, low skew, low jitter

zero delay buffer. It uses a phase lock loop (PLL)

technologytoalign, inbothphaseandfrequency, theREF

input with the CLKOUT signal. It is designed to distribute

high speed clocks in communication systems operating

at speeds from 10 to 133 MHz.

•

Zero input - output delay

Frequency range 10 - 133 MHz (3.3V)

5V tolerant input REF

High loop filter bandwidth ideal for Spread Spectrum

applications.

Less than 125 ps cycle to cycle Jitter

Skew controlled outputs

Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm

TSSOP packages

•

The ICS91309I provides synchronization between the

input and output. The synchronization is established via

CLKOUTfeedbacktotheinputofthePLL. Sincetheskew

between the input and output is less than +/- 350 pS, the

part acts as a zero delay buffer.

•

Skew:Group-to-Group:<215ps

Skew within Group: <100 ps

Industrial temperature range: -40°C to +85°C

ICS91309I has two banks of four outputs controlled by

two address lines. Depending on the selected address

line, bank B or both banks can be put in a tri-state mode.

In this mode, the PLL is still running and only the output

buffers are put in a high impedance mode. The test mode

shuts off the PLL and connects the input directly to the

output buffers (see table below for functionality).

Pin Configuration

REF

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

ICS91309I comes in a 16-pin 150 mil SOIC, SSOP or

4.40mm TSSOP package. In the absence of REF input,

thedevicewillenterapowerdownmode. Inthismode, the

PLL is turned off and the output buffers are pulled low.

Powerdownmodeprovidesthelowestpowerconsumption

for a standby condition.

GND

CLKB1

CLKB2

FS2

CLKB4

CLKB3

FS1

16 pin SSOP, SOIC & TSSOP

Block Diagram

Functionality

Ouput

Source Shutdown

PLL

FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT

Tristate

Driven

PLL

Tristate

PLL

Driven

PLL

Bypass

Mode

Driven

Bypass

Mode

Driven

Bypass

Mode

Driven

REF

PLL

0770B—02/02/04

12 3 4 5 6 7...9

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