FemtoClock® NG Jitter Attenuator
and Clock Synthesizer
8V19N491-36
Datasheet
Description
Features
The 8V19N491-36 is a fully integrated FemtoClock® NG jitter
attenuator and clock synthesizer. The device is designed as a
high-performance clock solution for conditioning and
frequency/phase management of wireless base station radio
equipment boards. The device is optimized to deliver excellent
phase noise performance as required in GSM, WCDMA, LTE, and
LTE-A radio board implementations. The device supports
JESD204B subclass 0 and 1 clocks.
▪ High-performance clock RF-PLL with support for JESD204B
▪ Optimized for low phase noise: -152.5dBc/Hz (800kHz offset;
245.76MHz clock)
▪ Integrated phase noise of 65fs RMS typical (12kHz–20MHz) at
737.28MHz
▪ Dual-PLL architecture
▪ First PLL stage with external VCXO for clock jitter attenuation
▪ Second PLL with internal FemtoClock NG PLL: 3686.4MHz
▪ Six output channels with a total of 19 outputs, organized in:
A two-stage PLL architecture supports both jitter attenuation and
frequency multiplication. The first stage PLL is the jitter attenuator
and uses an external VCXO for best possible phase noise
characteristics. The second stage PLL locks on the VCXO-PLL
output signal and synthesizes the target frequency.
— Four JESD204B channels (device clock and SYSREF
output) with two, four, and six outputs
— One clock channel with two outputs
— One VCXO output
The 8V19N491-36 supports the clock generation of
high-frequency clocks from the selected VCO and low-frequency
synchronization signals (SYSREF). SYSREF signals are internally
synchronized to the clock signals. Delay functions exist for
achieving alignment and controlled phase delay between system
reference and clock signals and to align/delay individual output
signals. The four redundant inputs are monitored for activity. Four
selectable clock switching modes are provided to handle clock
input failure scenarios. Auto-lock, individually programmable
output frequency dividers, and phase adjustment capabilities are
added for flexibility.
▪ Configurable integer clock frequency dividers
▪ Supported clock output frequencies include: 3686.4, 1843.2,
1228.8, 737.28, 614.4, 368.4, 307.2, 245.76, 153.6, 122.88,
and 61.44MHz
▪ Low-power LVPECL/LVDS outputs support configurable signal
amplitude, DC and AC coupling, and LVPECL, LVDS line
terminations techniques
▪ Phase delay circuits
— Clock phase delay with 256 steps of 271ps and a range of
0 to 69.173ns
The device is configured through a 3/4-wire SPI interface and
reports lock and signal loss status in internal registers and via a
lock detect (LOCK) output. Internal status bit changes can also be
reported via the nINT output. The 8V19N491-36 is ideal for driving
converter circuits in wireless infrastructure, radar/imaging, and
instrumentation/medical applications. The device is a member of
the high-performance clock family from Renesas.
— Individual SYSREF phase delay with 8 steps of 271ps
— Additional individual SYSREF fine phase delay with
eight 25ps steps
— Global SYSREF signal delay with 256 steps of 543ps and a
range of 0 to 138.346ns
▪ Redundant input clock architecture with four inputs including:
— Input activity monitoring
Typical Applications
▪ Wireless infrastructure applications: GSM, WCDMA, LTE, and
LTE-A
— Manual and automatic, fault-triggered clock selection
modes
— Priority controlled clock selection
▪ Ideal clock driver for jitter-sensitive ADC and DAC circuits
▪ Low-phase noise clock generation
▪ Ethernet line cards
— Digital holdover and hitless switching
— Differential inputs accept LVDS and LVPECL signals
▪ SYSREF generation modes include internal and external
trigger mode for JESD204B
▪ Radar and imaging
▪ Instrumentation and medical
▪ Supply voltage: 3.3V
▪ SPI Interface, 3/4 wire configurable
▪ SPI and control I/O voltage: 1.8V/3.3V (selectable)
▪ Package: 11 11 mm, 100-CABGA
▪ Temperature range: -40°C to +85°C
©2019-2023 Renesas Electronics Corporation
1
November 20, 2023
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