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8V19N478BDGI8 PDF预览

8V19N478BDGI8

更新时间: 2024-02-09 20:14:09
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
70页 1217K
描述
FemtoClock NG Jit ter At tenuator and Clock Synthesizer

8V19N478BDGI8 数据手册

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®
FemtoClock NG Jitter Attenuator  
8V19N478  
Datasheet  
and Clock Synthesizer  
Description  
Features  
High-performance clock RF-PLL:  
The 8V19N478 is a fully integrated FemtoClock NG jitter  
attenuator and clock synthesizer designed as a high-performance  
clock solution for conditioning and frequency/phase management  
of 10/40/100/400 Gigabit-Ethernet line cards. The device is  
optimized to deliver excellent phase noise performance as  
required to drive physical layer devices, and provides the clean  
clock frequencies of 625MHz, 500MHz, 312.5MHz, 250MHz,  
156.25MHz, and 125MHz.  
Optimized for low phase noise: -157.7dBc/Hz (1MHz offset;  
156.25MHz clock), design target  
Integrated phase noise, RMS (12kHz–20MHz): 73fs  
(typical), design target  
Dual-PLL architecture:  
1st-PLL stage with external VCXO for clock jitter attenuation  
2nd-PLL stage with internal FemtoClock NG PLL at  
A two-stage PLL architecture supports both jitter attenuation and  
frequency multiplication. The first stage PLL is the jitter attenuator,  
and uses an external VCXO for best possible phase noise  
characteristics. The second stage PLL locks on the VCXO-PLL  
output signal, and synthesizes the target frequency. This PLL has  
a VCO circuit at 2500MHz.  
2500MHz  
Four output banks with a total of 18 outputs, organized in:  
Three clock banks with one integer frequency divider and  
four differential outputs  
One clock bank with one fractional divider and six  
differential outputs  
The 8V19N478 generates the output clock signals from the VCO  
by frequency division. Four independent frequency dividers are  
available; three support integer-divider ratios, and one integer as  
well as fractional-divider ratios. Delay circuits can be used for  
achieving alignment and controlled phase delay between clock  
signals. The two redundant inputs are monitored for activity. Four  
selectable clock switching modes are provided to handle clock  
input failure scenarios. Auto-lock, individually programmable  
output frequency dividers, and phase adjustment capabilities are  
added for flexibility.  
One VCXO-PLL output bank with one selectable LVDS and  
two LVCMOS outputs  
Four output banks contain a phase delay circuit with steps of  
the VCO clock period (400ps)  
Supported clock output frequencies include:  
From the integer dividers: 2500MHz, 1250MHz, 625MHz,  
500MHz, 312.5MHz, 250MHz, 156.25MHz, and 125MHz  
From the fractional divider: 80–300MHz  
Low-power LVPECL and LVDS outputs support configurable  
signal amplitude, DC and AC coupling, and LVPECL, LVDS,  
and line termination techniques  
The device is configured through an I2C interface and reports lock  
and signal loss status in internal registers and via a lock detect  
(LOCK) output. Internal status bit changes can also be reported  
via the nINT output. The device is ideal for driving converter  
circuits in wireless infrastructure, radar/imaging, and  
Redundant input clock architecture:  
Two inputs  
Individual input signal monitor  
Digital holdover  
instrumentation/medical applications. The device is a member of  
the high-performance clock family from IDT.  
Manual and automatic clock selection  
Hitless switching  
Status monitoring and fault reporting:  
Typical Applications  
Sub 70fs – low phase noise clock generation  
10/40/100 Gigabit-Ethernet line cards  
Wireless Infrastructure  
Input signal status  
Hold-over and reference loss status  
Lock status with one status pin  
Mask-able status interrupt pin  
Voltage supply:  
Reference clock for ADC and DAC circuits  
Radar and Imaging  
Instrumentation and Medical  
Device core supply voltage: 3.3V  
Output supply voltage: 3.3V, 2.5V, or 1.8V  
I/O voltage: 1.8V or 3.3V (selectable), and 3.3V tolerant  
inputs when set to 1.8V  
Package: 11 11 1 mm ball pitch 100-FPBGA  
Temperature range: -40°C to +85°C  
©2018 Integrated Device Technology, Inc  
1
May 15, 2018  
 
 
 

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