®
FemtoClock NG Jitter Attenuator
8V19N470
Datasheet
and Clock Synthesizer
Description
Features
The 8V19N470 is a fully integrated FemtoClock® NG jitter attenuator
and clock synthesizer designed as a high-performance clock solution
for conditioning and frequency/phase management of wireless base
station radio equipment boards.
▪ High-performance clock RF-PLL
▪ Optimized for low phase noise: ≤150dBc/Hz (1MHz offset;
245.76MHz clock)
▪ Dual-PLL architecture
The device is optimized to deliver excellent phase noise
— 1st-PLL stage with external VCXO for clock jitter attenuation
performance as required in GSM, WCDMA, LTE, LTE-A radio board
implementations. A two-stage PLL architecture supports both jitter
attenuation and frequency multiplication. The first stage PLL is the
jitter attenuator and uses an external VCXO for best possible phase
noise characteristics. The second stage PLL locks on the VCXO-PLL
output signal and synthesizes the target frequency. This PLL has two
VCO circuits at 2949.12MHz and 2400MHz–2500MHz, respectively,
for enhanced frequency flexibility.
— 2nd-PLL stage with internal FemtoClock NG PLL at selectable
2949.12MHz and 2400MHz 2500MHz VCO
▪ Five output channels with a total of 11 outputs, organized in:
— Two clock channels with two differential outputs
— Two clock channels with three differential outputs
— One VCXO-PLL channel with one selectable LVDS/ two
LVCMOS outputs
▪ Each clock channel contains an integer output divider and a
The device generates the output clock signals from the selected
VCO by frequency division. Four independent integer frequency
dividers are available. Delay circuits can be used for achieving
alignment and controlled phase delay between clock signals. The
two redundant inputs are monitored for activity. Four selectable clock
switching modes are provided to handle clock input failure scenarios.
Auto-lock, individually programmable output frequency dividers and
phase adjustment capabilities are added for flexibility.
phase delay circuit with 512 steps of half of the VCO period
▪ Supported clock output frequencies include:
— From VCO-0: 2949.12MHz, 1474.56MHz, 983.04MHz,
491.52MHz, 368.64MHz, 122.88MHz
— From VCO-1: 2457.6MHz, 1228.8MHz, 614.4MHz, 307.2MHz,
153.6, 76.8MHz or 625MHz, 500MHz, 312.5MHz, 250MHz,
156.25MHz, and 125MHz
The device is configured through an SPI interface and reports PLL
lock and signal loss status in internal registers, PLL lock status is
also reported via two lock detect outputs. Internal status bit changes
can also be reported via the nINT output. The device is ideal for
driving converter circuits in wireless infrastructure, radar/imaging
and instrumentation/medical applications. The device is a member of
the high-performance clock family from IDT.
▪ Low-power LVPECL/LVDS outputs support configurable signal
amplitude, DC and AC coupling and LVPECL, LVDS line
terminations techniques
▪ Redundant input clock architecture
— Two inputs
— Individual input signal monitor
— Digital holdover
— Manual and automatic clock selection
— Hitless switching
Typical Applications
▪ Low phase noise clock generation, specifically for jitter-sensitive
▪ Status monitoring and fault reporting
— Input signal status
ADC and DAC circuits
▪ Wireless infrastructure applications: GSM, WCDMA, LTE, LTE-A
▪ Ethernet
— Lock status of each individual PLL (two status pins)
— Hold-over and reference loss status
— Mask-able status interrupt pin
▪ Voltage supply:
— Device core supply voltage: 3.3V
— Output supply voltage: 3.3V, 2.5V or 1.8V
— Digital control I/O voltage: 1.8V (3.3V tolerant)
— SPI control I/O voltage: 1.8V or 3.3V (selectable), 3.3V
tolerant inputs when set to 1.8V
▪ Package: 81-FPBGA (8 8 1.35 mm, 0.8mm ball pitch)
▪ Temperature range: -40°C to +85°C
©2017 Integrated Device Technology, Inc.
1
November 20, 2017
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