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8V18512IDGGREP PDF预览

8V18512IDGGREP

更新时间： 2024-09-30 20:55:31
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
36页 497K
描述
LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

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中文翻译

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8V18512IDGGREP 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：64
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：LVT
JESD-30 代码：R-PDSO-G64长度：17 mm
逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER位数：9
功能数量：2端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：6.8 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

8V18512IDGGREP 数据手册

 浏览型号8V18512IDGGREP的Datasheet PDF文件第2页浏览型号8V18512IDGGREP的Datasheet PDF文件第3页浏览型号8V18512IDGGREP的Datasheet PDF文件第4页浏览型号8V18512IDGGREP的Datasheet PDF文件第5页浏览型号8V18512IDGGREP的Datasheet PDF文件第6页浏览型号8V18512IDGGREP的Datasheet PDF文件第7页 
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SCBS790 − NOVEMBER 2003  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
Compatible With the IEEE Std 1149.1-1990  
(JTAG) Test Access Port and  
Boundary-Scan Architecture  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
DGG PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Enhanced Product-Change Notification  
†
Qualification Pedigree  
1
64  
63  
62  
61  
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33  
1CLKAB  
1LEAB  
1OEAB  
1A1  
1CLKBA  
1LEBA  
1OEBA  
1B1  
1B2  
GND  
1B3  
2
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Members of the Texas Instruments  
WidebusFamily  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
3
4
5
1A2  
GND  
1A3  
1A4  
1A5  
6
7
8
1B4  
1B5  
and Output Voltages With 3.3-V V  
)
CC  
9
D
D
Support Unregulated Battery Operation  
Down to 2.7 V  
10  
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25  
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31  
32  
V
V
CC  
CC  
1A6  
1A7  
1A8  
GND  
1A9  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B6  
1B7  
1B8  
GND  
1B9  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
D
D
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
B-Port Outputs of SN74LVTH182512 Device  
Has Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
SCOPE Instruction Set  
V
V
CC  
CC  
− IEEE Std 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
2A7  
2A8  
2A9  
GND  
2B7  
2B8  
2B9  
GND  
2OEBA  
2LEBA  
2CLKBA  
TDI  
− Parallel-Signature Analysis at Inputs  
− Pseudo-Random Pattern Generation  
From Outputs  
− Sample Inputs/Toggle Outputs  
− Binary Count From Outputs  
− Device Identification  
2OEAB  
2LEAB  
2CLKAB  
TDO  
TMS  
TCK  
− Even-Parity Opcodes  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and UBT are trademarks of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...36

中文翻译

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