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8V18502AIPMREP PDF预览

8V18502AIPMREP

更新时间: 2024-09-30 12:50:35
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路测试
页数 文件大小 规格书
42页 935K
描述
3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

8V18502AIPMREP 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.47
系列:LVTJESD-30 代码:S-PQFP-G64
JESD-609代码:e4长度:10 mm
逻辑集成电路类型:BOUNDARY SCAN REG BUS TRANSCEIVER湿度敏感等级:3
位数:9功能数量:2
端口数量:2端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):220传播延迟(tpd):6.8 ns
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

8V18502AIPMREP 数据手册

 浏览型号8V18502AIPMREP的Datasheet PDF文件第2页浏览型号8V18502AIPMREP的Datasheet PDF文件第3页浏览型号8V18502AIPMREP的Datasheet PDF文件第4页浏览型号8V18502AIPMREP的Datasheet PDF文件第5页浏览型号8V18502AIPMREP的Datasheet PDF文件第6页浏览型号8V18502AIPMREP的Datasheet PDF文件第7页 
ꢒ ꢓꢒ ꢎꢅ ꢍꢔꢆ ꢀꢕ ꢍꢁ ꢆ ꢏꢀꢆ ꢖ ꢏꢅ ꢗ ꢕꢏ  
SCAS744A − DECEMBER 2003 − REVISED JUNE 2004  
D
D
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup Resistors  
Enhanced Product-Change Notification  
B-Port Outputs of SN74LVTH182502A  
Device Have Equivalent 25-Series  
Resistors, So No External Resistors Are  
Required  
Qualification Pedigree  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Members of the Texas Instruments  
WidebusFamily  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
and Output Voltages With 3.3-V V  
D
D
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
SCOPE Instruction Set  
)
CC  
− IEEE Standard 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
D
Support Unregulated Battery Operation  
Down to 2.7 V  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
− Parallel-Signature Analysis at Inputs  
− Pseudorandom Pattern Generation From  
Outputs  
− Sample Inputs/Toggle Outputs  
− Binary Count From Outputs  
− Device Identification  
− Even-Parity Opcodes  
description/ordering information  
The SN74LVTH18502A and SN74LVTH182502A scan test devices, with 18-bit universal bus transceivers, are  
members of the Texas Instruments SCOPEtestability integrated-circuit family. This family of devices supports  
IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan  
access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type  
flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit  
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples  
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP  
in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
LQFP − PM  
LQFP − PM  
Tape and reel  
Tape and reel  
8V18502AIPMREP  
LH18502AEP  
−40°C to 85°C  
§
8V182502AIPMREP  
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available  
at www.ti.com/sc/package.  
Product Preview  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and UBT are trademarks of Texas Instruments.  
Copyright 2004, Texas Instruments Incorporated  
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ꢪꢧ ꢩ ꢧ ꢤ ꢥ ꢜ ꢥ ꢩ ꢟ ꢓ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

8V18502AIPMREP 替代型号

型号 品牌 替代类型 描述 数据表
74LVTH18502APMRG4 TI

完全替代

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18502APM TI

完全替代

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18502APMR TI

完全替代

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

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