Datasheet > 8T73S1802

8T73S1802

更新时间： 2023-12-20 18:46:20

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
25页	1169K
描述
1:2 Clock Fanout Buffer and Frequency Divider

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

8T73S1802 数据手册

1:2 Clock Fanout Buffer and

Frequency Divider

8T73S1802

Datasheet

Description

Features

The 8T73S1802 is a fully integrated clock fanout buffer and

frequency divider. The input signal is frequency-divided and then

fanned out to one differential LVPECL and one LVCMOS output.

Each of the outputs can select its individual divider value from the

range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and

SEL1 (3-level logic) are available to select the frequency dividers

and the output enable/disable state. The single-ended LVCMOS

output is phase-delayed by 650ps to minimize coupling of

LVCMOS switching into the differential output during its signal

transition.

• High-performance fanout buffer clock and fanout buffer

• Input clock signal is distributed to one LVPECL and one

LVCMOS output

• Configurable output dividers for both LVPECL and LVCMOS

outputs

• Supports clock frequencies up to 1000MHz (LVPECL) and up to

200MHz (LVCMOS)

• Flexible differential input supports LVPECL, LVDS and CML

• V_BBgenerator output supports single-ended input signal

applications

The 8T73S1802 is optimized to deliver very low phase noise

clocks. The V_BBoutput generates a common-mode voltage

reference for the differential clock input so that connecting the V_BB

pin to an unused input (nCLK) enables to use of single-ended input

signals. The extended temperature range supports wireless

infrastructure, telecommunication and networking end equipment

requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V

power supply. The device is a member of the high-performance

clock family from IDT.

• Optimized for low phase noise

• 650ps delay between LVCMOS and LVPECL minimizes coupling

between outputs

• Supply voltage: 3.3V or 2.5V

• -40°C to 85°C ambient operating temperature

• 16 VFQFPN package (3 x 3 mm)

Block Diagram

Pin Assignment

÷1

CLK

÷2

÷4

÷8

V_{CCO_QB}

SEL0

GND

SEL1

nCLK

nQA

8T73S1802

Bias Generator

V_CC-1.3V

V_BB

GND

8XXXXXX

Pullup

SEL0

SEL1

Control

16-pin, 3mm x 3mm VFQFPN Package

January 21, 2018

12 3 4 5 6 7...25

下载PDF

与8T73S1802相关器件

型号	品牌	描述	获取价格	数据表
8T73S1802_17	IDT	1:2 Clock Fanout Buffer and Frequency Divider	获取价格
8T73S1802_18	IDT	1:2 Clock Fanout Buffer and Frequency Divider	获取价格
8T73S1802NLGI	IDT	1:2 Clock Fanout Buffer and Frequency Divider	获取价格
8T73S1802NLGI/W	IDT	1:2 Clock Fanout Buffer and Frequency Divider	获取价格
8T73S1802NLGI8	IDT	1:2 Clock Fanout Buffer and Frequency Divider	获取价格
8T73S208	IDT	2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer	获取价格