Datasheet > 8P391208

8P391208

更新时间： 2024-10-01 14:58:27

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
40页	1053K
描述
Low Additive Jitter 2:8 Buffer with Universal Differential Outputs

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8P391208 数据手册

Low Additive Jitter 2:8 Buffer with

Universal Differential Outputs

8P391208

Datasheet

Description

Features

• Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS

reference clocks

The 8P391208 is intended to take 1 or 2 reference clocks, select

between them, using a pin selection and generate up to 8 outputs

that are the same as the reference frequency.

• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz

(up to 1GHz when configured into HCSL output mode at 3.3V)

8P391208 supports two output banks, each with its own power

supply. All outputs in one bank would generate the same output

frequency, and each bank can be individually controlled for output

type or output enable.

• Select which of the two input clocks is to be used as the reference

clock for which bank via pin selection

• Generates 8 differential outputs

• Differential outputs selectable as LVPECL, LVDS, CML or HCSL

• CML mode supports two different voltage swings

The device can operate over the -40°C to +85°C temperature range.

• Differential outputs support frequencies from 1PPS to 700MHz

(up to 1GHz when configured into HCSL output mode at 3.3V)

• Outputs arranged in 2 banks of 4 outputs each

• Each bank supports a separate power supply of 3.3V, 2.5V or

1.8V

• Controlled by 3-level input pins

• Input mux selection control pin

• Control inputs are 3.3V-tolerant for all core voltages

• Output noise floor of -153dBc/Hz at 156.25MHz

• Core voltage supply of 3.3V, 2.5V or 1.8V

• -40°C to +85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Block Diagram

QA0

nQA0

QA1

nQA1

CLK_SEL

QA2

nQA2

QA3

CLK0

nCLK0

nQA3

QB0

nQB0

CLK1

nCLK1

QB1

nQB1

QB2

nQB2

QB3

nQB3

IOA

Logic

IOB

February 3, 2023

12 3 4 5 6 7...40

中文翻译

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